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[Other resource] fifo

Description: 高速FIFO，verilog设计。速度高达130Mhz
Platform: | Size: 107881 | Author: 王龙波 | Hits:

[Other resource] FIFO

Description: verilog开发的FIFO，经过验证，有完整版本的测试程序，经典之作
Platform: | Size: 1955 | Author: 屠宁杰 | Hits:

[Embeded-SCM Develop] 异步fifo的两种经典设计

Description: 异步fifo的两种经典设计，英文文章，里面含有verilog源代码
Platform: | Size: 220577 | Author: handsomexun | Hits:

[SourceCode] 采用格雷码的FIFO控制模块（verilog）

Description: 异步FIFO常用于存储、缓冲在两个异步时钟之间的数据传输。在异步电路中，由于时钟之间周期和相位完全独立，因而数据的丢失概率不为零。如何设计一个高可靠性、高速的异步FIFO电路便成为一个难点。本例采用格雷码方式，用verilog语言实现了异步FIFO控制，大大降低误码率，提高了可靠性。
Platform: | Size: 5440 | Author: hangman_102@126.com | Hits:

[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个

Description: 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
Platform: | Size: 43008 | Author: 立立 | Hits:

[Other Embeded program] FIFO_v

Description: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Platform: | Size: 175104 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 高速FIFO，verilog设计。速度高达130Mhz-High-speed FIFO, verilog design. Speed up to 130MHz
Platform: | Size: 107520 | Author: | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Verilog语言编写，把FPGA配置成一个fifo-The use of Verilog language, the FPGA configuration into a fifo
Platform: | Size: 19456 | Author: achesser | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: verilog开发的FIFO，经过验证，有完整版本的测试程序，经典之作-Verilog development FIFO, after verification, a complete version of the test procedure, classic
Platform: | Size: 2048 | Author: 屠宁杰 | Hits:

[VHDL-FPGA-Verilog] FIFO_Example2

Description: 用Verilog语言写的FPGA FIFO，仅供参考。-Verilog language used to write the FPGA FIFO, for informational purposes only.
Platform: | Size: 1024 | Author: yangyu | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
Platform: | Size: 2048 | Author: 杨帆 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] asynfifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
Platform: | Size: 25600 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo用Verilog hdl的实现，这是一个比较常用的源码，文档中有很详细的注释，初学者应该可以看懂。-implementation using Verilog hdl usb, this is a common source, the document had a very detailed notes, beginners should understand.
Platform: | Size: 6144 | Author: zhulyan580086 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: verilog实现fifo，ise中仿真，chipscope调试-verilog achieve fifo, ise in the simulation, chipscope debugging
Platform: | Size: 4930560 | Author: xiangxj | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
Platform: | Size: 8192 | Author: fan | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
Platform: | Size: 2048 | Author: 大黄黄黄 | Hits:

[Fax program] fifo

Description: Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)
Platform: | Size: 4649984 | Author: gankl | Hits:

[VHDL-FPGA-Verilog] verilog实例 [43项]

Description: 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
Platform: | Size: 190464 | Author: hayto | Hits:

[VHDL-FPGA-Verilog] 异步FIFO

Description: 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)
Platform: | Size: 2048 | Author: wt2110 | Hits:
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