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[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[Communication] uart_verilog

Description: verilog & vhdl以及外国公司的应用说明。-Verilog
Platform: | Size: 148480 | Author: 丁路杰 | Hits:

[VHDL-FPGA-Verilog] FIR_1

Description: FIR滤波器的verilog实现，实现6级流水线的程序设计。-FIR filter Verilog, has implemented six lines of program design.
Platform: | Size: 1024 | Author: 李甫 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 完成一个FIR数字滤波器的设计。要求： 1、 基于直接型和分布式两种算法。 2、 输入数据宽度为8位，输出数据宽度为16位。 3、 滤波器的阶数为16阶，抽头系数分别为h[0]=h[15]=0000，h[1]=h[14]=0065，h[2]=h[13]=018F，h[3]=h[12]=035A，h[4]=h[11]=0579，h[5]=h[10]=078E，h[6]=h[9]=0935，h[7]=h[8]=0A1F。 -Completion of a FIR digital filter design. Requirements: one, based on the direct type and distributed two algorithms. 2, input data width of 8, the output data width of 16. 3, filter order of 16 bands, tap coefficients for h [0] = h [15] = 0000, h [1] = h [14] = 0065, h [2] = h [13] = 018F , h [3] = h [12] = 035A, h [4] = h [11] = 0579, h [5] = h [10] = 078E, h [6] = h [9] = 0935, h [7] = h [8] = 0A1F.
Platform: | Size: 5120 | Author: fredyu | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。 -Verilog procedures, to achieve 4-order filter fir-filter.
Platform: | Size: 1024 | Author: 左麟 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ　ＨＤＬ，顶层文件ＦＩＲ．Ｖ-FPGA realization of digital filters, based on the hardware description language VERILOG HDL, the top-level file FIR. V
Platform: | Size: 5120 | Author: YP | Hits:

[Documents] fir

Description: 线性相位FIR滤波器（17阶）的VHDL语言设计 功能很强大，很好用-Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use
Platform: | Size: 148480 | Author: jingjing | Hits:

[DSP program] fir

Description: 本设计用verilog代码实现FIR滤波器！-Verilog code of the design FIR filters to achieve!
Platform: | Size: 1024 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 用verilog设计的FIR滤波器。滤波器需要很快的处理速度，所以采用了wallace树算法，超前进位加法器-The FIR filter is designed with verilog. To improve the process speed, wallace tree and fast-carrylook-aheadarithmetic were used.
Platform: | Size: 324608 | Author: simeon chan | Hits:

[VHDL-FPGA-Verilog] beta

Description: Fir verilog code implemented to find out the output of fir filter
Platform: | Size: 1024 | Author: dheeru | Hits:

[Other] FIR

Description: This implementation of Low power Finite Impulse response filter design and implemented in Verilog-This is implementation of Low power Finite Impulse response filter design and implemented in Verilog
Platform: | Size: 5120 | Author: Ravindra | Hits:

[VHDL-FPGA-Verilog] fir

Description: 用状态机编写的FIR，verilog代码，已经经过仿真-With the state machine written in FIR, verilog code, and has passed through simulation
Platform: | Size: 1024 | Author: 于水洋 | Hits:

[VHDL-FPGA-Verilog] fir

Description: fir滤波器，Verilog语言写的，容易看懂-fir filter, Verilog language written in easy to understand
Platform: | Size: 2048 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog编的fir滤波器，可以自己输入参数序列，产生滤波波形-Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
Platform: | Size: 1024 | Author: lifei | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[Software Engineering] FIR

Description: FIR filter using verilog code
Platform: | Size: 2150400 | Author: Karama | Hits:

[VHDL-FPGA-Verilog] fir

Description: 比较简单的16位fir滤波器，16阶，Verilog编写-Simple 16-bit fir filter, 16 bands, Verilog prepared
Platform: | Size: 2048 | Author: 刘安 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir滤波器的简单实现，主要用于学习与理解(Simple implementation of the fir filter, mainly for learning and understanding)
Platform: | Size: 1024 | Author: 未曾走远 | Hits:

[VHDL-FPGA-Verilog] FIR设计实现sgh

Description: FIR滤波FPGA实现 ，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Platform: | Size: 25600 | Author: 韩冻少 | Hits:
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