Search - UART using verilog

[Com Port] uart

Description: this a Uart source code using Verilog.
Platform: | Size: 10294 | Author: Daniel Zhang | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
Platform: | Size: 10240 | Author: lfy | Hits:

[Other Embeded program] uart

Description: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.-Simple UART functions in the compiler under QUARTUS4.0 through using VERILOG HDL preparation.
Platform: | Size: 1024 | Author: 不是 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现的串口异步通信，适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
Platform: | Size: 1126400 | Author: 王权 | Hits:

[VHDL-FPGA-Verilog] uart

Description:
Platform: | Size: 14336 | Author: 顾向南 | Hits:

[Com Port] uart

Description: this a Uart source code using Verilog.
Platform: | Size: 10240 | Author: Daniel Zhang | Hits:

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[Com Port] UART

Description: 带有自适应功能的UART，是用VERILOG编写的源码，包括测试文件，与大家分享-Adaptive function with UART, are prepared using VERILOG source code, including test papers, to share with you
Platform: | Size: 4096 | Author: wangdali | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart using verilog hdl
Platform: | Size: 12288 | Author: imran ahmed | Hits:

[Com Port] uart

Description: 采用verilog语言描述的uart串口驱动程序主要用于调试-Using verilog language to describe the uart serial port driver is mainly used for debugging
Platform: | Size: 407552 | Author: lynn | Hits:

[VHDL-FPGA-Verilog] UART

Description: A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
Platform: | Size: 765952 | Author: xzorox | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用Quartus ii软件，编程语言为Verilog语言，实现UART通信协议，FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
Platform: | Size: 1435648 | Author: 冰色火焰 | Hits:

[VHDL-FPGA-Verilog] UART

Description: uart接口，使用Verilog编写，适用于各类FPGA-uart interface written using Verilog, applicable to all FPGA
Platform: | Size: 3072 | Author: 潘映波 | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog编写的UART模块,波特率19200，系统时钟100MHz,x3s50an应用成功-UART module using Verilog
Platform: | Size: 1024 | Author: xhly | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

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[Com Port] uart

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[VHDL-FPGA-Verilog] FPGA_UART

[VHDL-FPGA-Verilog] verilog-UART-Controler

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[VHDL-FPGA-Verilog] uart

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