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Description: 硬件uart源程序verilog HDL,即相关文档-hardware UART Verilog HDL source, that the relevant documents
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Size: 343040 |
Author: 陈正一 |
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Description: 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver/transmitter (UART) can be programmed to control computer attached to the serial device interface microchips. Details, provide it to the computer RS-High ... UART also provide a certain number of data buffer, computer equipment and serial data stream can maintain the same speed.
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Size: 9216 |
Author: 李志 |
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Description: UART verilog hdl 实现-UART Verilog HDL achieve
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Size: 3072 |
Author: |
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Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
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Size: 10240 |
Author: cyberworm |
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Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
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Size: 5120 |
Author: 李文文 |
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Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
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Size: 294912 |
Author: 刘索山 |
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Description: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.-Simple UART functions in the compiler under QUARTUS4.0 through using VERILOG HDL preparation.
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Size: 1024 |
Author: 不是 |
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Description: UART 串口程序,verilog语句,很好的实现了UART的通信功能!-UART serial procedures, verilog statement, very good communication to achieve the UART function!
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Size: 182272 |
Author: 王和国 |
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Description: 用Verilog实现的串口异步通信,适用于RS232-Using Verilog realization of serial asynchronous communication, applied to RS232
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Size: 1126400 |
Author: 王权 |
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Description: 一个通用串口的verilog源程序,包含发送和接收模块-A universal serial Verilog source code, including sending and receiving modules
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Size: 53248 |
Author: typhooncome |
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Description: this a Uart source code using Verilog.
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Size: 10240 |
Author: Daniel Zhang |
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Description: verilog设计的UART事例,适合于初学者-Verilog UART design examples, suitable for beginners
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Size: 154624 |
Author: 张扬 |
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Description: 用FPGA实现了RS232异步串行通信,所用语言是VHDL,另外本人还有Verilog的欢迎交流学习,根据RS232 异步串行通信来的帧格式,在FPGA发送模块中采用的每一帧格式为:1位开始位+8位数据位+1位奇校验位+1位停止位,波特率为2400。由设置的波特率可以算出分频系数,具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
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Size: 1024 |
Author: saibei007 |
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Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
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Size: 10240 |
Author: 陈强 |
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Description: uart异步串口通信协议的源代码,用vhdl语言编写,并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
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Size: 10240 |
Author: 阿军 |
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Description: UART verilog TX/RX OpenCores share
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Size: 5120 |
Author: richman |
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Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
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Size: 3072 |
Author: 赵云 |
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Description: UART verilog 代码, 内置CPU接口方式,支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
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Size: 15360 |
Author: dingyy |
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Description: uart 的verilog源码,希望对大家有用!(UART Verilog source hope useful for all!)
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Size: 1024 |
Author: qcleo
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Description: verilog实现串口通讯,包括verilog代码和testbench代码(verilog serial communication, including the verilog code and testbench Code)
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Size: 791552 |
Author: 代工 |
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