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[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 36519 | Author: 戴鹏 | Hits:

[Other resource] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206883 | Author: 张清平 | Hits:

[Other resource] usb_phy

Description: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Platform: | Size: 10088 | Author: liuzefu | Hits:

[Other resource] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196910 | Author: lious | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件
Platform: | Size: 213167 | Author: 高杰 | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[VHDL-FPGA-Verilog] usb_phy

Description: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Platform: | Size: 10240 | Author: liuzefu | Hits:

[VHDL-FPGA-Verilog] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196608 | Author: lious | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
Platform: | Size: 212992 | Author: 高杰 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[USB develop] usb20

Description: 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
Platform: | Size: 205824 | Author: wx | Hits:

[VHDL-FPGA-Verilog] VERILOG-USB2.0IP-core

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
Platform: | Size: 220160 | Author: king | Hits:

[VHDL-FPGA-Verilog] USB2.0

Description: usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
Platform: | Size: 3567616 | Author: PETER | Hits:

[VHDL-FPGA-Verilog] usbtrace[1].v1.1

Description: usb2.0 trace verilog code very useful
Platform: | Size: 1048576 | Author: skh5515 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: | Size: 64512 | Author: AmazingEric | Hits:

[VHDL-FPGA-Verilog] USB2.0-IP-core

Description: 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
Platform: | Size: 200704 | Author: 柳同学 | Hits:

[VHDL-FPGA-Verilog] usb2.0-verilog-hdl

Description: usb2.0协议层的verilog hdl实现-usb2.0 protocol layer implementation verilog hdl
Platform: | Size: 20480 | Author: liguangwen | Hits:

[VHDL-FPGA-Verilog] USB2.0的IP核（详细verilog源码和文档）

Description: USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
Platform: | Size: 195584 | Author: kelvinlu | Hits:

[VHDL-FPGA-Verilog] FPGA_USB2.0设计

Description: 把FX2配置成从FIFO的模式， 配置为单片机工作时钟24M，端点2输出，字节1024，端点6输入，字节1024，信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟，也就是让FX2给我们的设计当做时钟源，输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input, byte 1024, signal all set to low level and so on. Our module drive clock is configured as an internal output clock, that is, let FX2 give our design as the clock source, and output a clock with the largest configuration clock 48M.)
Platform: | Size: 430080 | Author: 硅渣渣 | Hits:
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