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[File Operate] VHDL tutor n exam

Description: verilog hdl. for igginner. tutorial in word file1 KAMPATE
Platform: | Size: 93279 | Author: 输入要 | Hits:

[SourceCode] pcounter

Description: /2 /3 /4 ...... /n
Platform: | Size: 964 | Author: choushuguang@yahoo.com.cn | Hits:

[VHDL-FPGA-Verilog] 数据结构c描述习题集答案

Description: 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Platform: | Size: 111616 | Author: tutu | Hits:

[File Format] VHDL tutor n exam

Description: verilog hdl. for igginner. tutorial in word file1 KAMPATE
Platform: | Size: 93184 | Author: 输入要 | Hits:

[VHDL-FPGA-Verilog] xapp616

Description: A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx-A. Huffman implementation reference desig n in both VHDL and Verilog is provided by the Xili nx
Platform: | Size: 13312 | Author: | Hits:

[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14336 | Author: 许茹芸 | Hits:

[Other] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113664 | Author: mingming | Hits:

[Other] Verilog

Description: verilog的简要教程 基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以 是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[VHDL-FPGA-Verilog] mesh_dft

Description: 自己写一个关于维mesh结构的noc网络，verilog，仿真结果无误。-Write their own structure on the noc-dimensional mesh network, verilog, accurate simulation results.
Platform: | Size: 95232 | Author: 巴音 | Hits:

[Crack Hack] BasicRSA_latest.tar

Description: RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key
Platform: | Size: 5120 | Author: nb | Hits:

[VHDL-FPGA-Verilog] divide

Description: It is n-bit sequential divider in verilog language
Platform: | Size: 1024 | Author: Lisha | Hits:

[VHDL-FPGA-Verilog] nxn_multiplier

Description: Verilog module for hardware N x N multiplier using generate keyword.
Platform: | Size: 1024 | Author: ifusmell | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[VHDL-FPGA-Verilog] division

Description: Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB-Verilog n-bit Division using datapath and controller for COMPUTER ARCHITECT LAB
Platform: | Size: 4096 | Author: RQG | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 基于FPGA的SOPC的学习教程，本人找了N久才找到的，希望能帮助到有需要的朋友-SOPC FPGA-based learning tutorial, I looked for a long time to find N, and intend to help a friend in need
Platform: | Size: 468992 | Author: Andy Lao | Hits:

[VHDL-FPGA-Verilog] adder_fa4bit

Description: 4 bit full adder verilog code n test bench
Platform: | Size: 27648 | Author: M. Usman | Hits:

[VHDL-FPGA-Verilog] 86verilog

Description: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求-　W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design requirement .
Platform: | Size: 15360 | Author: 任伟 | Hits:

[VHDL-FPGA-Verilog] Introduction-to-Verilog

Description: Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, -Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, Verilog 1364
Platform: | Size: 191488 | Author: zhujizhen | Hits:

[VHDL-FPGA-Verilog] N-bits-by-M-bits

Description: 这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器-This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier
Platform: | Size: 3072 | Author: 祖兴水 | Hits:

[Other] dff-n-d-latch

Description: Dlatch and D Flipflp code with testbench in Verilog
Platform: | Size: 1024 | Author: pravat | Hits:
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