Description: 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses Platform: |
Size: 635323 |
Author:张稀楠 |
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Description: 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses Platform: |
Size: 634880 |
Author:张稀楠 |
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Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用
双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、
与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data）
为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和
满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations. Platform: |
Size: 378880 |
Author:lsg |
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Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。
实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线 上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。
实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频 率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment. Platform: |
Size: 1225728 |
Author:Emma |
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Description: FSK/PSK调制顶层文件
，正弦波模块
，正弦波模块初始化文件
，振幅调整及波形选择模块
，频率显示值地址产生模块
，频率步进键核心模块
，弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the frequency of the displayed value address generator module, the frequency of stepping key core modules, bouncing the elimination of circuit Platform: |
Size: 27648 |
Author:libing |
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Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input. Platform: |
Size: 98304 |
Author:宫逢源 |
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Description: 基于EPM7128的数字合成信号发生器（DDS）设计。通过对EPM7128编程，组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized Platform: |
Size: 354304 |
Author:xiaoyu |
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Description: 基于ROM的正弦波发生器的设计
一．实验目的
1. 学习VHDL的综合设计应用
2. 学习基于ROM的正弦波发生器的设计
二．实验内容
设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based sine wave generator design
1. Purpose of the experiment
1. VHDL Integrated Design and Application of Learning
2. Learning ROM-based sine wave generator design
2. Experimental content
ROM-based sine wave generator design, its compilation, simulation.
Specific requirements:
1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules
Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB.
3. The 50MHz input clock. Platform: |
Size: 17408 |
Author:爱好 |
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Description: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk. Platform: |
Size: 4096 |
Author:cccs |
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Description: VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer Platform: |
Size: 6144 |
Author:林琳 |
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