Search - bcd - CodeBus

[SCM] pic

Description: pic子程序集，加减法，BCD码转换，键盘子程序-pic
Platform: | Size: 96256 | Author: 绽放 | Hits:

[VHDL-FPGA-Verilog] verilog_program

Description: 各种初学Verilog者需要练习的实例代码集锦，包含加法器，BCD计数器，2分频，交通灯等等！-Beginners need to practice a variety of examples of Verilog code highlights, including the adder, BCD counters, 2 frequency, traffic lights and more!
Platform: | Size: 32768 | Author: lyh | Hits:

[VHDL-FPGA-Verilog] bcd_to_binary

Description: bcd to binary verilog
Platform: | Size: 4096 | Author: hyuma | Hits:

[Other] BCD

Description: 模为 60 的 BCD码加法计数器，采用verilog语言编写。-BCD code module for the addition of 60 counters, using verilog language.
Platform: | Size: 1024 | Author: kevin | Hits:

[assembly language] 16-BCD

Description: 汇编语言实验设计关于16进制数转换为BCD码形式-Assembly language, the number of experimental design on the 16 hexadecimal form converted to BCD code
Platform: | Size: 1024 | Author: TTT | Hits:

[VHDL-FPGA-Verilog] B_to_D

Description: 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
Platform: | Size: 1009664 | Author: 程光 | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

[assembly language] bcd

Description: 能够实现2个bcd码相乘，并未把结果存到已知的存储单元中-Bcd code to achieve two multiply, did not save the results to the known storage unit
Platform: | Size: 4096 | Author: ljn | Hits:

[VHDL-FPGA-Verilog] bin2bcd

Description: 用来将二进制的信号转化成BCD码形式的信号，用来在数码管上显示相应的数字。-To the binary signal into BCD code in the form of signals, used in the digital display the corresponding number.
Platform: | Size: 252928 | Author: da | Hits:

[VHDL-FPGA-Verilog] part2

Description: Implement a 3-digit BCD counter. Display the contents of the counter on the 7-segment displays, HEX2− 0. Derive a control signal, from the 50-MHz clock signal provided on the DE2 board, to increment the contents of the counter at one-second intervals. Use the pushbutton switch KEY0 to reset the counter to 0.
Platform: | Size: 552960 | Author: echo | Hits:

[VHDL-FPGA-Verilog] 2BCD

Description: 二进制转BCD码 verilog hdl Quartus II 9.0sp2 编译通过所有的文件-Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
Platform: | Size: 286720 | Author: 王冠 | Hits:

[VHDL-FPGA-Verilog] Counter

Description: 计数器 QuartusⅡ 10进制计数器 CLKIN为时钟输入端，CLR为清零端，Y[3..0]为四位二进制输出（BCD 码形式），CLKOUT为10进制计数器进位输出端 -Counter
Platform: | Size: 29696 | Author: duopk | Hits:

[VHDL-FPGA-Verilog] bcd_to_7segmentos

Description: bcd to 7 segments display tested on xboard xilinx, all code developed on vhdl
Platform: | Size: 602112 | Author: carlos | Hits:

[VHDL-FPGA-Verilog] 999jisq

Description: 一个能从0~999计数的 bcd码数码管电路-A count from 0 to 999 digital control circuit bcd code
Platform: | Size: 86016 | Author: 黄国猛 | Hits:

[Windows Develop] bcd

Description: WINDOWS 7 和 XP启动BCD编辑工具!-WINDOWS 7 and XP start BCD editor!
Platform: | Size: 155648 | Author: th1nk | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用VHDL语言实现的二进制到BCD码和格雷码的转换，程序通读性比较好。-VHDL language with the binary code and Gray code to BCD conversion, the program read through is better.
Platform: | Size: 1024 | Author: 周波 | Hits:

[assembly language] bcd

Description: 三字节转BCD双字节十六进制整数转换成双字节ＢＣＤ码整数.txt-Three-byte transfer byte BCD integer into a double-byte hexadecimal integer BCD code. Txt
Platform: | Size: 1024 | Author: zxs | Hits:

[VHDL-FPGA-Verilog] BCD

Description: ROM vhdl for binary to BCD
Platform: | Size: 1024 | Author: K1000 | Hits:

[SCM] 02-BCD-Conv

Description: 关于单片机bcd的应用程序，希望对大家有帮助！-Bcd on the MCU application, we want to help!
Platform: | Size: 18432 | Author: 杨镇宁 | Hits:

[SCM] 07-BCD-NEG

Description: 关于单片机bcd neg的应用程序，希望对大家有帮助！-SCM bcd neg on application, we want to help!
Platform: | Size: 25600 | Author: 杨镇宁 | Hits:

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[SCM] pic

[VHDL-FPGA-Verilog] verilog_program

[VHDL-FPGA-Verilog] bcd_to_binary

[Other] BCD

[assembly language] 16-BCD

[VHDL-FPGA-Verilog] B_to_D

[VHDL-FPGA-Verilog] vhdlcoder

[assembly language] bcd

[VHDL-FPGA-Verilog] bin2bcd

[VHDL-FPGA-Verilog] part2

[VHDL-FPGA-Verilog] 2BCD

[VHDL-FPGA-Verilog] Counter

[VHDL-FPGA-Verilog] bcd_to_7segmentos

[VHDL-FPGA-Verilog] 999jisq

[Windows Develop] bcd

[VHDL-FPGA-Verilog] vhdl

[assembly language] bcd

[VHDL-FPGA-Verilog] BCD

[SCM] 02-BCD-Conv

[SCM] 07-BCD-NEG

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