Search - convolution VHDL

[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6873 | Author: 潘华林 | Hits:

[Other resource] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6276 | Author: 李超 | Hits:

[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6144 | Author: 潘华林 | Hits:

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[Special Effects] ImageConvolution_src

Description: Convolution of images allows for image alterations that enable the creation of new images from old ones. 此源码包含十分详尽的Bitmap位图卷积实现方法-Convolution of images allows for image alt erations that enable the creation of new images from old ones. This source includes very detailed Bitmap bitmap deconvolution method
Platform: | Size: 21504 | Author: | Hits:

[source in ebook] RSencode

Description: 包含RS（10，8）的verilog源程序，加法器的verilog源程序，卷积码的verilog源程序-Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
Platform: | Size: 1024 | Author: bai | Hits:

[VHDL-FPGA-Verilog] juanjiqi

Description: 这是一个卷积器的设计，源码值得好好地学习-This is a convolution design, source code should be a good learning
Platform: | Size: 19456 | Author: lzc | Hits:

[VHDL-FPGA-Verilog] conv2

Description: Program to implement convolution of two signals.
Platform: | Size: 1024 | Author: Prads | Hits:

[VHDL-FPGA-Verilog] conv3

Description: Program to implement convolution through VHDL-Program to implement convolution through VHDL...
Platform: | Size: 1024 | Author: Prads | Hits:

[VHDL-FPGA-Verilog] Convolution

Description:
Platform: | Size: 104448 | Author: 龚阳 | Hits:

[VHDL-FPGA-Verilog] baseband_verilog

Description: verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器-verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
Platform: | Size: 26624 | Author: 刘新 | Hits:

[Communication] conv_vhdl

Description: 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[Other] k_9_rate_1-2_VHDL

Description: viterbi generator its very good for convolution
Platform: | Size: 24576 | Author: morpheus35 | Hits:

[VHDL-FPGA-Verilog] convolution_calculator_4_bits

Description: convolution is important and is widely used in digital signal processing.For example, in LTI system. Input two sequences of 8-bit 2 s complement signed numbers with length 2~8. the input values range is -128~127.
Platform: | Size: 5476352 | Author: chen-che,wemg | Hits:

[VHDL-FPGA-Verilog] juanji

Description: 采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用-Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging
Platform: | Size: 2048 | Author: wangminmin | Hits:

[VHDL-FPGA-Verilog] VD-vhdl-Code

Description: this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
Platform: | Size: 7168 | Author: shishir | Hits:

[VHDL-FPGA-Verilog] convolution

Description: convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
Platform: | Size: 152576 | Author: ant | Hits:

[VHDL-FPGA-Verilog] convolution

Description: 卷积严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
Platform: | Size: 22138880 | Author: Lu Li | Hits:

[VHDL-FPGA-Verilog] 卷积交织器解交织器设计

Description: 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row, and then read out by column; deinterleaving process is the first data written by the column, then read by line. It is characterized by a simple structure, but the data delay time is long, and the required memory is relatively large.)
Platform: | Size: 753664 | Author: 一个+ | Hits:

[Documents] 基于VHDL卷积交织器的设计与实现

Description: 基于VHDL卷积交织器的设计与实现(1)(Design and implementation of convolution Interleaver Based on VHDL)
Platform: | Size: 214016 | Author: 大的幅度 | Hits:

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[Embeded-SCM Develop] 卷积码、CRC

[Other resource] gongcehngsheji_477-2

[Embeded-SCM Develop] 卷积码、CRC

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

[Special Effects] ImageConvolution_src

[source in ebook] RSencode

[VHDL-FPGA-Verilog] juanjiqi

[VHDL-FPGA-Verilog] conv2

[VHDL-FPGA-Verilog] conv3

[VHDL-FPGA-Verilog] Convolution

[VHDL-FPGA-Verilog] baseband_verilog

[Communication] conv_vhdl

[Other] k_9_rate_1-2_VHDL

[VHDL-FPGA-Verilog] convolution_calculator_4_bits

[VHDL-FPGA-Verilog] juanji

[VHDL-FPGA-Verilog] VD-vhdl-Code

[VHDL-FPGA-Verilog] convolution

[VHDL-FPGA-Verilog] convolution

[VHDL-FPGA-Verilog] 卷积交织器解交织器设计

[Documents] 基于VHDL卷积交织器的设计与实现

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