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[Other resource] verilog-som

Description: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Platform: | Size: 5857 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] entropy_coding

Description: 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His description of coding (entropy coding) for image compression test files are encoded
Platform: | Size: 19456 | Author: 周信均 | Hits:

[VHDL-FPGA-Verilog] verilog-som

Description: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Platform: | Size: 5120 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] 9.1_ONE_PULSE

Description: 基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 　　9.1.1 由系统功能描述时序关系 　　9.1.2 流程图的设计 　　9.1.3 系统功能描述 　　9.1.4 逻辑框图 　　9.1.5 延时模块的详细描述及仿真 　　9.1.6 功能模块Verilog-HDL描述的模块化方法 　　9.1.7 输入检测模块的详细描述及仿真 　　9.1.8 计数模块的详细描述 　　9.1.9 可编程单脉冲发生器的系统仿真 　　9.1.10 可编程单脉冲发生器的硬件实现 　　9.1.11 关于电路设计中常用的几个有关名词 -based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Description logic diagram 9.1.5 9.1.4 Delay Module detailed description and simulation of 9.1. 6 functional modules Verilog-HDL description of the modular input method detection module 9.1.7 detailed 9.1.8 Description and Simulation module counting a detailed description 9.1.9 programmable pulse generator system 9.1.10 Simulation programmable pulse generator hardware on the circuit design 9.1.11 Constant Some of the terminology
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[Graph program] sobel

Description: 图像边缘检测的VERILOG实现，能准确检测图像边缘-Image Edge Detection of Verilog realize that can accurately detect image edge
Platform: | Size: 589824 | Author: 李永杰 | Hits:

[VHDL-FPGA-Verilog] smallkeybaord

Description: 用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行-Written using Verilog 4* 4 keypad keys detection procedures. The project has been compiled. Directly in the development of Atera DE1 Fpga board run
Platform: | Size: 1594368 | Author: 王乔 | Hits:

[VHDL-FPGA-Verilog] gps_jiance

Description: 合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
Platform: | Size: 1024 | Author: 远方 | Hits:

[VHDL-FPGA-Verilog] tb

Description: 检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify
Platform: | Size: 1024 | Author: ly | Hits:

[Crack Hack] A-PAINLESS-GUIDE-TO-CRC-ERROR-DETECTION-ALGORITHMS

Description: A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC校验理论与实践的经典教程，Ross写的。-A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS CRC checksum of the classic theory and practice tutorials, Ross wrote.
Platform: | Size: 184320 | Author: haoz | Hits:

[Software Engineering] fre_ctrl

Description: 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL description of the behavior and structure of a description of the realization of frequency meter 8, 4 0 detection circuit principle of the amendment note
Platform: | Size: 14336 | Author: 黎明 | Hits:

[Documents] FPGA

Description: 基于 FPGA 的运动目标检测系统的研究与开发 希望有哪位朋友需要-FPGA-based Moving Target Detection System for a friend who would like to have necessary
Platform: | Size: 7645184 | Author: maolei | Hits:

[Special Effects] syndetect

Description: 帧同步检测，verilog代码 是同步保护的经典范例-frame detection, verilog code
Platform: | Size: 1024 | Author: leng | Hits:

[VHDL-FPGA-Verilog] edge_detection

Description: edge detection algorithm in verilog HDL, along with test bench file. compiled in modelsim6.1
Platform: | Size: 34816 | Author: yahyajan | Hits:

[VHDL-FPGA-Verilog] miller

Description: 用ISE编写的VERILOG语言的米勒解码器的检测部分，检测四种解码信号。程序通过综合，但是仿真结果有点偏差，欢迎高手指点。-ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice welcome.
Platform: | Size: 37888 | Author: kinki | Hits:

[Communication] Descrambler

Description: ofdm中相位检测的Verilog程序，很不错，可以在Xilinxfpga上运行。-phase detection in ofdm Verilog program, very good, you can Xilinxfpga run.
Platform: | Size: 136192 | Author: 吴雷 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] Edge-detection

Description: 多个边缘检测sobel算子的verilog程序模块。-Multiple edge detection sobel operator verilog program modules
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] 5B6B-codec

Description: verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, decoding module, and error detection module, and through modesim simulation.
Platform: | Size: 4096 | Author: 林海全 | Hits:

[Other] Edge Detection Filters

Description: Edge Detection Filters
Platform: | Size: 508928 | Author: ssaeed | Hits:

[VHDL-FPGA-Verilog] Verilog的边沿检测技术_设计源代码

Description: 波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
Platform: | Size: 36864 | Author: gxgone | Hits:
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