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[Symbian] buffers

Description: buffer example. buffer example. buffer example.
Platform: | Size: 2048 | Author: 刘正贤 | Hits:

[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1024 | Author: 夏社 | Hits:

[SCM] C8051F040_CAN_block

Description: This program configures the external memory interface and CAN to receieve data in a FIFO buffer and store the data in XRAM. Meant to receive data from another CAN device.-This program configures the external memory interface and CAN to receieve data in a FIFO buffer and store the data in XRAM. Meant to receive data from another CAN device.
Platform: | Size: 11264 | Author: sf | Hits:

[SCM] SerialFIFOForC51

Description: 89S52上实现51单片机的串口FIFO功能。即串口的收和发均采用了FIFO作为缓冲。相信这个程序有助于单片机的新手编写串口操作-89S52 achieve 51 MCU Serial FIFO functions. Serial admission that the hair and are used as a FIFO buffer. I believe this program helps prepare newcomers MCU serial operation
Platform: | Size: 32768 | Author: 陈根潮 | Hits:

[Other] ztemplbase

Description: 基于deque实现的队列模板，可用作各种数据类型的先进先出缓冲。-based cohort achieved templates can be used as the various types of data FIFO buffer.
Platform: | Size: 2048 | Author: 蓝文纪 | Hits:

[uCOS] queue_arm_drive

Description: AMR7 队列驱动。 LPC2138基于ucos的中间件,FIFO发送队列缓冲，信号量同步，用于发送批量数据. -AMR7 cohort driven. Based on the LPC2138 OUT middleware, FIFO buffer this cohort, the signal synchronized, used to send bulk data.
Platform: | Size: 49152 | Author: 高明 | Hits:

[Windows Develop] vrb-0.5.1.tar

Description: The Virtual Ring Buffer (VRB) is an implementation of a character FIFO ring buffer.
Platform: | Size: 40960 | Author: 刘少麟 | Hits:

[Windows Develop] fifo

Description: 一个FIFO先入先出BUFFER的C程序。用户可以设置BUFFER大小，并通过write_fifo()和read_fifo()函数分别写入和读出数据-A FIFO FIFO BUFFER of C procedures. Users can set the BUFFER size, and through write_fifo () and read_fifo () function, respectively, and write读出数据
Platform: | Size: 1024 | Author: 韓建棟 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
Platform: | Size: 2048 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
Platform: | Size: 2048 | Author: falcon_cq | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: A First in first out buffer in Verilog
Platform: | Size: 1024 | Author: Ran | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
Platform: | Size: 183296 | Author: luosheng | Hits:

[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[VHDL-FPGA-Verilog] fifo89

Description: 先进先出FIFO缓冲器，8位字宽，9位字深，很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Platform: | Size: 269312 | Author: gdfrg | Hits:

[SCM] uart

Description: Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup for various different mode as required by your application. In this tutorial I will show you how to configure the USART in a most common configuration and simply send and receive data. Later on I will give you my library of USART that can further ease you work. It will be little complicated (but more useful) as it will have a FIFO buffer and will use interrupt to buffer incoming data so that you are free to anything in your main() code and read the data only when you need. All data is stored into a nice FIFO(first in first out queue) in the RAM by the ISR.
Platform: | Size: 1024 | Author: sstefan | Hits:

[VHDL-FPGA-Verilog] FIFO24_CS8416[1]

Description: Fifo buffer vhdl code
Platform: | Size: 1024 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
Platform: | Size: 432128 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
Platform: | Size: 4096 | Author: 刀刀 | Hits:

[Data structs] ring-buffer

Description: 在通信程序中，经常使用环形缓冲区作为数据结构来存放通信中发送和接收的数据。环形缓冲区是一个先进先出的循环缓冲区，可以向通信程序提供对缓冲区的互斥访问-In the communications program, frequently used as a ring buffer data structure to store communications to send and receive data. FIFO ring buffer is a circular buffer, the communication program can provide mutually exclusive access to the buffer
Platform: | Size: 34816 | Author: 江立 | Hits:
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