Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - lfsr verilog

Search list

[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 162816 | Author: 夏沫 | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[VHDL-FPGA-Verilog] rng

Description: verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
Platform: | Size: 94208 | Author: Alex | Hits:

[Crack Hack] lfsr

Description: 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[Other] lfsr

Description: 用LSFR实现计数功能，可以减少对寄存器和少一个加法器，涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
Platform: | Size: 61440 | Author: liuzefu | Hits:

[VHDL-FPGA-Verilog] profiles

Description: source code of counter,ram,lfsr etc
Platform: | Size: 2048 | Author: narsimha | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[Other] lfsr.v.tar

Description: linear feedback shift register for generator in verilog code for random sequence generation.
Platform: | Size: 2048 | Author: balu | Hits:

[VHDL-FPGA-Verilog] BIST

Description: A simple BIST in VHDL. It contains a LFSR with an SISR.
Platform: | Size: 405504 | Author: bommeren | Hits:

[VHDL-FPGA-Verilog] lfsr

Description: 此实验介绍了伪随机序列的产生原理，并用verilog语言将其编码实现，有详细的代码备注-This experiment introduces the principle of pseudo-random sequence and its encoded with the verilog language implementation, a detailed code Notes
Platform: | Size: 76800 | Author: 飞扬奇迹 | Hits:

[VHDL-FPGA-Verilog] lfsr

Description: linear feedback shift register verilog code
Platform: | Size: 4096 | Author: zcos123 | Hits:

[VHDL-FPGA-Verilog] lfsr

Description: simple PRBS generator using verilog hdl
Platform: | Size: 1024 | Author: karthik | Hits:

[Program doc] LFSR

Description: practical example using verilog and vhdl by xilinx
Platform: | Size: 854016 | Author: ali | Hits:

[VHDL-FPGA-Verilog] verilog-lfsr-updown-counter

Description: Verilog 8 bit LFSR Up-Down Counter
Platform: | Size: 10240 | Author: cmags | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: Verilog code for an 8-bit LFSR
Platform: | Size: 1024 | Author: baboy | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 这是基于FPGA开发板NEXTS3的一个verilog程序，是一个线性反馈移位寄存器LFSR,可用来生成伪随机数-This is based on the FPGA development board NEXTS3 a verilog program, is a linear feedback shift register LFSR, can be used to generate pseudo random Numbers
Platform: | Size: 859136 | Author: 黄志宇 | Hits:

[VHDL-FPGA-Verilog] hidejj

Description: 实现线性反馈移位寄存器的verilog实现(lfsr use verilog for the zip)
Platform: | Size: 3205120 | Author: 嘿嘿702 | Hits:

[VHDL-FPGA-Verilog] pseudo_random

Description: 基于vivado Verilog的伪随机数发生器，采用LFSR算法，并对其进行了升级，使用反馈级联的思想，从最大周期为2^n提升为原来的3-5倍(Based on vivado Verilog pseudo random number generator, using LFSR algorithm, and upgrade it, using the idea of feedback cascade, from the maximum cycle of 2^n to 3-5 times the original)
Platform: | Size: 1889280 | Author: 9901tzh | Hits:

[VHDL-FPGA-Verilog] lab2B(4)LFSR

Description: 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
Platform: | Size: 1024 | Author: 电聪骑风 | Hits:

[VHDL-FPGA-Verilog] BIC

Description: this project for adaptive schme techniques by using LFSR design projects
Platform: | Size: 175104 | Author: king of VLSI | Hits:
« 12 »

CodeBus www.codebus.net