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Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
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Size: 808948 |
Author: 萧飒 |
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Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
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Size: 808960 |
Author: 萧飒 |
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Description: 四间隔频率变化，并循环输出50~51ms之间的频率。-Four-interval frequency changes and the cycle between 50 ~ 51ms output frequency.
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Size: 1024 |
Author: 孙敬辉 |
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Description: Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read, erase, and
program operations
— Separate VCCQ for 5 volt I/O tolerance
n Automated Program and Erase
— Page program: 512 + 16 bytes
— Block erase: 8 K + 256 bytes
n Block architecture
— 8 Kbyte blocks + 256 byte spare area
(separately erasable, readable, and programmable)
— 512 byte page + 16 byte spare area for ECC and other
system overhead information
n Fast read and program performance (typical values)
— Read: < 7 μs initial, < 50 ns sequential
— Program: 200 μs (full page program at 400 ns/byte)
— Erase: < 2 ms/8 Kbyte block
n Pinout and package
— Industry Standard NAND compatible pinout with 8-bit
I/O bus and control signals
— TSOP-II 44/40 pin package (standard and reverse)
with copper lead frame for higher reliability
— 40-ball FBGA package provides higher reliability-Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read, erase, and
program operations
— Separate VCCQ for 5 volt I/O tolerance
n Automated Program and Erase
— Page program: 512+ 16 bytes
— Block erase: 8 K+ 256 bytes
n Block architecture
— 8 Kbyte blocks+ 256 byte spare area
(separately erasable, readable, and programmable)
— 512 byte page+ 16 byte spare area for ECC and other
system overhead information
n Fast read and program performance (typical values)
— Read: < 7 μs initial, < 50 ns sequential
— Program: 200 μs (full page program at 400 ns/byte)
— Erase: < 2 ms/8 Kbyte block
n Pinout and package
— Industry Standard NAND compatible pinout with 8-bit
I/O bus and control signals
— TSOP-II 44/40 pin package (standard and reverse)
with copper lead frame for higher reliability
— 40-ball FBGA package provides higher reliability
Platform: |
Size: 847872 |
Author: enyou |
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Description: 体育用记时秒表，显示MS，S,MIN功能-watch
Platform: |
Size: 419840 |
Author: 李磊 |
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Description: 数字秒表的VHDL课程设计 通过硬件测试 精确到ms 最大可计时为24小时 -Digital stopwatch curriculum design through the VHDL hardware testing is accurate to ms maximum time of 24 hours
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Size: 436224 |
Author: li |
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Description: Doxygen是一个文档生成系统，可用于C++, C, Java, Objective-C, Python, IDL (Corba and Microsoft flavors), Fortran, VHDL, PHP, C#, and to some extent D.
它能从一系列代码源文件中生成在线文档(HTML格式)和离线文档(Latex格式) 。也支持生成RTF (MS-Word), PostScript, PDF, 压缩HTML(chm), and Unix man pages等格式的文档。文档直接从源码中提取而成，便于维护。
Doxygen能很方便地从源码中提取出代码的组织结构，和代码中变量的关系图。这只需要配置好doxygen，一切都自动生成。这在大型代码发布时相当有用。-failed to translate
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Size: 4141056 |
Author: newuserid |
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Description: 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
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Size: 3072 |
Author: 周峰 |
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Description: 用vhdl语言写的频率计，可以实现1khz到1Mhz，当低于1Khz时可实现测周期单位为ms，测量精度达到99 ，用数码管动态显示-Vhdl language written with the frequency meter can be achieved 1khz to 1Mhz, when less than 1Khz cycle when unit for detecting ms, 99 accuracy, dynamic display with digital control
Platform: |
Size: 4096 |
Author: 李彦松 |
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Description: 本设计基于数字频率合成技术,采用正弦查找表实现波形产生.直接数字频率合成技术（DDS）是一种先进的电路结构，能在全数字下对输出信号频率进行精确而快速的控制，DDS技术还在解决输出信号频率增量选择方面具有很好的应用，DDS所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续、输出相位噪声低和可以产生任意波形等诸多优点。 文中介绍了DDS的基本原理，对DDS的质谱及其散杂抑制进行了分析。程序设计采用超高速硬件描述语言VHDL描述DDS,在此基础上设计了正弦波、三角波、方波等信号发生器，。完成了软件和硬件的设计，以及实验样机的部分调试。-The design is based digital frequency synthesizer technology, using a sine lookup table to achieve waveform generation. Direct digital frequency synthesis (DDS) is an advanced circuit structure can fully digital output signal frequency under precise and fast control, DDS technology also solve the incremental output signal frequency selection signal having a very good application, DDS generated by high frequency resolution, frequency switching speed, phase-continuous frequency switching time, low phase noise output and can generate arbitrary waveforms, and many other advantages . This paper introduces the basic principles of the DDS, DDS MS for its bulk inhibition were analyzed. Programming using ultra high-speed hardware description language VHDL description DDS, on the basis of the design of the sine wave, triangle wave, square wave signal generator. Completed part of debugging software and hardware design, and the experimental prototype.
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Size: 4485120 |
Author: 冯阳 |
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