Description: verilog HDL原码
一种简单的同步FIFO原码,可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated Platform: |
Size: 1467 |
Author:zxz |
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Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all. Platform: |
Size: 20480 |
Author:daiowen |
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Description: verilog HDL原码
一种简单的同步FIFO原码,可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated Platform: |
Size: 1024 |
Author:zxz |
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Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序,erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~ Platform: |
Size: 69632 |
Author:张勇奇 |
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Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench Platform: |
Size: 2048 |
Author:彭帅 |
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Description: 使用Verilog编写的同步FIFO,可通过设置程序中的DEPTH设置FIFO的深度,FIFO_WRITE_CLOCK上升沿向FIFO中写入数据,
FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising edge to the FIFO write data, FIFO_READ_CLOCK rising edge of read data. This procedure on the upper FIFO operation simple and practical. Platform: |
Size: 1024 |
Author:张键 |
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Description: 实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码-NAND Flash control access and control of the synchronous FIFO verilog code Platform: |
Size: 6144 |
Author:alliance |
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Description: 同步fifo的verilog代码,很好的资料,值得学习-Synchronous fifo verilog code, very good information, it is worth learning Platform: |
Size: 1024 |
Author:李军 |
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Description: 一个用verilog实现的同步fifo设计,压缩包里有word介绍设计中各信号的作用-Achieve a synchronous fifo with verilog design, compression bag has the role of word describes the design of the signals Platform: |
Size: 120832 |
Author:csy |
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Description: 该源码包是同步fifo的Verilog语言模型,主要包括2个部分:同步fifo控制模块、测试文件。(The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.) Platform: |
Size: 1024 |
Author:叶古
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Description: 自己编写的同步和异步FIFO的verilog代码,验证过,有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.) Platform: |
Size: 2048 |
Author:大黄黄黄 |
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Description: 一些采用verilog描述的数字功能模块,有常见的同步异步FIFO,RAM等模块,适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning) Platform: |
Size: 190464 |
Author:hayto |
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