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[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 294912 | Author: 刘索山 | Hits:

[Other Embeded program] UART

Description: 一个通用串口的verilog源程序，包含发送和接收模块-A universal serial Verilog source code, including sending and receiving modules
Platform: | Size: 53248 | Author: typhooncome | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] uart

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[Com Port] uart

Description: this a Uart source code using Verilog.
Platform: | Size: 10240 | Author: Daniel Zhang | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-Verilog] mini-uart

Description: Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Platform: | Size: 253952 | Author: serein | Hits:

[VHDL-FPGA-Verilog] uart

Description: Verilog编写的UART程序源代码。测试成功。支持字符串发送-UART prepared Verilog source code. Successful test. Support string sent
Platform: | Size: 1548288 | Author: 卢山 | Hits:

[Software Engineering] uart

Description: UART schematic and code
Platform: | Size: 149504 | Author: buhuhubau | Hits:

[VHDL-FPGA-Verilog] Transmitter

Description: UART Transmitter Verilog Code
Platform: | Size: 202752 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] Receiver

Description: UART Receiver Verilog Code
Platform: | Size: 193536 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] uart

Description: this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
Platform: | Size: 4096 | Author: tri | Hits:

[VHDL-FPGA-Verilog] uart-code-Verilog

Description: uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
Platform: | Size: 10240 | Author: 李明纬 | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART verilog 代码， 内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
Platform: | Size: 15360 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog HDL 入门学习的源代码。 包括双向语法，计数器，状态机，锁存器，uart等-Introduction to learning verilog HDL source code. Including two-way grammar, counters, state machines, latches, uart, etc.
Platform: | Size: 3072 | Author: 鲁东 | Hits:
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