Search - uart vhdl asynchronous

[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme
Platform: | Size: 10240 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] uart_vhdl

Description: vhdl的异步串口代码，可以方便以致在不同的FPGA中-asynchronous serial VHDL code, can easily result in different FPGA in
Platform: | Size: 18432 | Author: 李冰 | Hits:

[VHDL-FPGA-Verilog] uart_for_MCU

Description: 用VHDL为MCU编写的可用UART-通用异步收发器程序-Using VHDL for the MCU can be used to prepare the UART-Universal Asynchronous Receiver Transmitter procedures
Platform: | Size: 1024 | Author: pc repair | Hits:

[VHDL-FPGA-Verilog] UART_VHDL

Description: URAT异步通信接口的VHDL描述，可综合-URAT asynchronous communication interface VHDL description can be integrated
Platform: | Size: 667648 | Author: luyingc | Hits:

[VHDL-FPGA-Verilog] uart

Description: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Platform: | Size: 212992 | Author: 朱兆斌 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] uart

Description: M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Platform: | Size: 18432 | Author: lc | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[VHDL-FPGA-Verilog] miniUART

Description: 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
Platform: | Size: 9216 | Author: 甘甜 | Hits:

[Crack Hack] micro-UARTsource_V

Description: UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allows for full-duplex serial link communications.
Platform: | Size: 5120 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[VHDL-FPGA-Verilog] uart

Description: 基于vhdl的串口通信模块，即异步收发机，可实现单片机核fpga的收发串口通信，遵从rs232协议，已经调试过，很不错的资源-Vhdl-based serial communication module, that is, asynchronous transceiver can achieve single-chip transceiver nuclear fpga serial communication, rs232 to comply with the agreement, has been testing, it is a good resource
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[Com Port] UART

Description: 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the procedures and instructions, validate through, with good stability and reference value!
Platform: | Size: 2269184 | Author: Kerwin | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart - universal asynchronous receicer and transmitter source code using VHDL
Platform: | Size: 1930240 | Author: nagarjuna reddy | Hits:

[VHDL-FPGA-Verilog] UART2

Description: 基于SPARTAN-3E的与计算机的异步串行通信，可根据需要更改波特率等等。-SPARTAN-3E based on the asynchronous serial communication with the computer, according to the need to change the baud rate and so on.
Platform: | Size: 365568 | Author: 姚武 | Hits:

[VHDL-FPGA-Verilog] uart-

Description: 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
Platform: | Size: 30720 | Author: mike | Hits:

[VHDL-FPGA-Verilog] A-Simplified-VHDL-UART

Description: In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord. Serial communication is often used either to control or to receive data from an embedded microprocessor. Serial communication is a form of I/O in which the bits of a byte begin transferred appear one after the other in a timed sequence on a single wire. Serial communication has become the standard for intercomputer communication. In this lab, we ll try to build a serial link between 8051 and PC using RS232.
Platform: | Size: 374784 | Author: mezzich | Hits:

[Other] UART.ZIP

Description: Lattice用VHDL开发的UART（UARTUniversalAsynchronousReceiverTransmitter）控制器SourceCode -UART Universal Asynchronous Receiver Transmitter SourceCode
Platform: | Size: 388096 | Author: FinFET | Hits:

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[VHDL-FPGA-Verilog] 标准的串口通讯设计VHDL

[VHDL-FPGA-Verilog] uart_vhdl

[VHDL-FPGA-Verilog] uart_for_MCU

[VHDL-FPGA-Verilog] UART_VHDL

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart(Verilog)

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] miniUART

[Crack Hack] micro-UARTsource_V

[VHDL-FPGA-Verilog] uart8

[Industry research] UART_DESIGN

[VHDL-FPGA-Verilog] uart

[Com Port] UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART2

[VHDL-FPGA-Verilog] uart-

[VHDL-FPGA-Verilog] A-Simplified-VHDL-UART

[Other] UART.ZIP

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