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[VHDL-FPGA-Verilog] examples

Description:
Platform: | Size: 9216 | Author: 111111 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] Frequency_divider

Description: 用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
Platform: | Size: 134144 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog HDL 编写的时钟分频器-prepared by the clock divider verilog HDL
Platform: | Size: 672768 | Author: luoxs | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[VHDL-FPGA-Verilog] Downloads

Description: clock divider in verilog for FPGA use
Platform: | Size: 1024 | Author: harini | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] DCM

Description: xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
Platform: | Size: 2599936 | Author: wangyu | Hits:

[VHDL-FPGA-Verilog] fangbo

Description: 一个可切换分频的时钟分频器的verilog语言，可根据具体情况修改参数实现不同的分频-A switchable clock divider divider verilog language, modify the parameters according to the specific circumstances of different sub-frequency
Platform: | Size: 1312768 | Author: 李彦超 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 利用verilog语言在fpga上实现不同分频器的设计，适合初学者学习-Verilog language in different divider on the fpga design, suitable for beginners to learn
Platform: | Size: 87040 | Author: houxiaoshuai | Hits:

[VHDL-FPGA-Verilog] verilog-code

Description: 都是verilog代码：多路选择器代码，储存器代码，时钟分频器代码，串并转换电路代码，香农扩展运算代码，ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
Platform: | Size: 2439168 | Author: ponyma | Hits:

[Software Engineering] Clk_Divider

Description: System Verilog Clock Divider module done with impementation, contains the implementes modules inside too.
Platform: | Size: 3072 | Author: souhaku | Hits:

[VHDL-FPGA-Verilog] div_clk

Description: verilog实现任意时钟分频，简单明了，打开modelsim-change directroy-do sim .do 即可-Achieve any clock divider, simple, open modelsim-change directroy-do sim. Do to
Platform: | Size: 40960 | Author: | Hits:

[Algorithm] Clock-Divider

Description: this verilog program, Clock Divider, can be compiled successfully by Altera and ModelSIM.
Platform: | Size: 155648 | Author: anxar | Hits:

[VHDL-FPGA-Verilog] counter

Description: 同步清零的可逆计数器，带时钟分频 Verilog HDL语言编写-Synchronous clear reversible counter with clock divider Verilog HDL language
Platform: | Size: 336896 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] frequency-divider

Description: 用VERILOG 语言写的数控分频器，可能输入时钟信号实现任意整数倍的分频，-NC divider, with the words written in VERILOG HDL, can achieve any integer multiple of the input clock frequency, contains the entire project file.
Platform: | Size: 491520 | Author: zyb | Hits:

[VHDL-FPGA-Verilog] clk_generator

Description: 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
Platform: | Size: 390144 | Author: duzengquan | Hits:

[VHDL-FPGA-Verilog] divider-achieved-by-verilog

Description: 该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
Platform: | Size: 2048 | Author: daruili | Hits:

[VHDL-FPGA-Verilog] 7_1

Description: 电路端口为：异步清零输入端口rst，输入时钟clk_in，输出时钟clk_out。并分别采用两种以上的方法实现。(Frequency divider circuit port is: Asynchronous Clear input port rst, input clock clk_in, output clock clk_out. And use two or more methods to achieve.)
Platform: | Size: 271360 | Author: 白学 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
Platform: | Size: 2048 | Author: 饭饭哒 | Hits:
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