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[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 36519 | Author: 戴鹏 | Hits:

[Other resource] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206883 | Author: 张清平 | Hits:

[Other resource] usb_phy

Description: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Platform: | Size: 10088 | Author: liuzefu | Hits:

[Other resource] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196910 | Author: lious | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件
Platform: | Size: 213167 | Author: 高杰 | Hits:

[USB develop] USB2.0_rtl_ipcore_verilog

Description:
Platform: | Size: 62464 | Author: 王椿棠 | Hits:

[USB develop] USB2_chip

Description: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Platform: | Size: 35840 | Author: 戴鹏 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Platform: | Size: 206848 | Author: 张清平 | Hits:

[VHDL-FPGA-Verilog] usb_phy

Description: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Platform: | Size: 10240 | Author: liuzefu | Hits:

[Other Embeded program] USB2.0_Slave_FIFO_ASync

Description: This an USB2.0 chip CY7C68013 Configuraion Example for Slave FIFO mode with "async" mode.
Platform: | Size: 123904 | Author: MyName | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
Platform: | Size: 212992 | Author: 高杰 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档-Complete Verilog language developed by USB2.0 IP core source code, including documentation
Platform: | Size: 206848 | Author: 陈润 | Hits:

[USB develop] usb20

Description: 通用接口usb2.0的verilog开发代码-Common interface usb2.0 development of the verilog code
Platform: | Size: 205824 | Author: wx | Hits:

[VHDL-FPGA-Verilog] VERILOG-USB2.0IP-core

Description: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
Platform: | Size: 220160 | Author: king | Hits:

[VHDL-FPGA-Verilog] USB2.0

Description: usb2.0 fpga程序 用vhdl语言编写 quartus环境实现 -usb2.0 fpga using vhdl language program quartus environment to achieve
Platform: | Size: 3567616 | Author: PETER | Hits:

[VHDL-FPGA-Verilog] CY7C68013

Description: USB2.0的Verilog实现，含有完整的FPGA代码-Use Verilog to implement the USB2.0 protcol
Platform: | Size: 600064 | Author: XCP | Hits:

[VHDL-FPGA-Verilog] usbtrace[1].v1.1

Description: usb2.0 trace verilog code very useful
Platform: | Size: 1048576 | Author: skh5515 | Hits:

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

Description: USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
Platform: | Size: 64512 | Author: AmazingEric | Hits:

[VHDL-FPGA-Verilog] USB2.0-IP-core

Description: 用verilog 写的USB2.0，含源码。从别处找来的，不敢独享，希望对大家有帮助-Written by verilog USB2.0, including source code. Recruited from elsewhere, and not exclusive, we want to help
Platform: | Size: 200704 | Author: 柳同学 | Hits:

[VHDL-FPGA-Verilog] USB2.0的IP核（详细verilog源码和文档）

Description: USB2.0的IP核开发.代码可以直接使用已经验证过(USB2.0 IP kernel development. Code can be used directly, has been verified)
Platform: | Size: 195584 | Author: kelvinlu | Hits:
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