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Description: TLC5510 VHDL控制程序 基于VHDL语言，实现对高速A/D器件TLC5510控制-TLC5510 VHDL control procedures based on the VHDL language, to achieve high-speed A / D control device TLC5510
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Size: 3351 |
Author: 少龙 |
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Description: This a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of the language is covered (about 95％).
You may use this booklet for your own personal learning purposes.
You may not use it for profit (eg, selling copies of it, using it in a
course for which people pay, etc). If you want to make use of it
beyond these conditions, contact me and we can come to some
arrangement.
-This a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%). You may use this boo klet for your own personal learning purposes. Y ou may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these co nditions. contact me and we can come to some arrangement.
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Size: 245947 |
Author: 罗春晖 |
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Description: This is a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of the language is covered (about 95％).
-This is a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%).
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Size: 238174 |
Author: 罗春晖 |
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Description: 用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制，所用的开发软件是ＱＵＡＴＴＵＳ６.０-using VHDL A / D conversion of the state machine control, used in the development of software is QUATTUS6.0
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Size: 166462 |
Author: 吴林煌 |
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Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
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Size: 3688067 |
Author: fuhao |
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Description: VHDL 8位无符号除法器 试验报告
计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。
其实现方法是，将除法器分为两个状态：等待状态与运算状态。
开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。
-VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
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Size: 82944 |
Author: aa |
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Description:
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Size: 3072 |
Author: 少龙 |
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Description: 数字电压表
AD芯片：
采用8位串行A/D转换器ADC0832。
● 8位分辨率，逐次逼近型，基准电压为 5V
● 5V单电源供电
● 输入模拟信号电压范围为 0～5V
● 有两个可供选择的模拟输入通道
显示：
使用三个数码管。
显示范围：
0.00 － 5.10 （单位：V）
连接方式：
AD_CLK → P1.0
AD_DAT → P1.1
AD_CS → P3.4
模拟输入 → CH0
(AD_DAT = DO + DI)
ADC0832输出最大转换值＝FFH (255)
设定最大测量值＝5.1V
255X=5.1 X=0.02 即先乘2再除以100
（小数点放在第三位数码管）- Digital voltmeter
AD chip: Uses 8 serial A/D switch ADC0832.* 8 resolution,
gradually approaching, the datum voltage is 5V* the 5V single power
source power supply* input simulated signal voltage scope is 0 ~ 5V*
has two to be possible to supply the choice the analog input channel
Demonstrated: Uses three digital tubes.
Demonstrates the scope: 0.00- 5.10 (unit: V)
Connection way:
AD_CLK-> P1.0 AD_DAT-> P1.1 AD_CS-> P3.4 analog input-> CH0
(AD_DAT = DO DI)
ADC0832 output biggest transformation value = FFH (255)
establishes greatest observed value = 5.1V 255X=5.1 X=0.02 namely
first to ride 2 to eliminate again by 100 (decimal point puts on third
digital tube)
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Size: 7168 |
Author: lmhit |
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Description: This a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of the language is covered (about 95％).
You may use this booklet for your own personal learning purposes.
You may not use it for profit (eg, selling copies of it, using it in a
course for which people pay, etc). If you want to make use of it
beyond these conditions, contact me and we can come to some
arrangement.
-This a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%). You may use this boo klet for your own personal learning purposes. Y ou may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these co nditions. contact me and we can come to some arrangement.
Platform: |
Size: 245760 |
Author: 罗春晖 |
Hits:
Description: This is a set of notes I put together for my Computer Architecture
class in 1990. Students had a project in which they had to model a
microprocessor architecture of their choice. They used these notes to
learn VHDL. The notes cover the VHDL-87 version of the language.
Not all of the language is covered (about 95％).
-This is a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%).
Platform: |
Size: 237568 |
Author: 罗春晖 |
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Description: 用ＶＨＤＬ实现Ａ／Ｄ转换的状态机的控制，所用的开发软件是ＱＵＡＴＴＵＳ６.０-using VHDL A/D conversion of the state machine control, used in the development of software is QUATTUS6.0
Platform: |
Size: 165888 |
Author: 吴林煌 |
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Description: VHDL设计——16位A/D转换器的设计-VHDL Design-- 16-bit A/D converter design
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Size: 5120 |
Author: 钱伟康 |
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Description: VHDL设计——16位D/A转换器的设计-VHDL Design-- 16-bit D/A converter design
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Size: 5120 |
Author: 钱伟康 |
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Description: 常用双通道24位A/D芯片cs5550串口输出信号单片机读取程序-common dual-channel 24-bit A/D chip cs5550 serial output signal SCM reader
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Size: 1024 |
Author: yk |
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Description: 基于fpga和sopc的用VHDL语言编写的EDA采样高速A/D的存储示波器-FPGA and SOPC based on the use of VHDL language EDA sampling high-speed A/D of the storage oscilloscope
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Size: 58368 |
Author: 多幅撒 |
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Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
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Size: 3687424 |
Author: hawd |
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Description: A/D采样控制模块设计
A/D采样控制模块负责控制外部ADC0809芯片多路模拟输入量的选通以及实现对A/D采样过程的合理控制。此部分的设计根据《EDA技术与VHDL》P211——P212的例8-2编写，所不同的是这里将书中“ADDA<=1”的赋值语句改为“ADDA <=EN”，EN是所设置的输入按键用来控制INO与IN1间的通道选择。
-A/D sampling control module designed A/D sampling control modules responsible for controlling external ADC0809 chip multi-channel analog input, as well as the amount of strobe to achieve A/D sampling the reasonable control of the process. This part of the design under the EDA technology and VHDL P211- P212 preparation of the cases of 8-2, the difference is that here the book ADDA <= 1 of the assignment changed to ADDA <= EN , EN is the set of input buttons used to control between INO and IN1 channel selection.
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Size: 1024 |
Author: xuye |
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Description: 基于FPGA的A/D转换
可以用quartusII仿真-FPGA-based A/D conversion can be used quartusII Simulation
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Size: 5702656 |
Author: |
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Description: 用vhdl编写的D触发器，锁存器等，不需帐号就可自由下载此源码-VHDL prepared using D flip-flops, latches and so on, no account can be a free download this source
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Size: 1024 |
Author: daniel |
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Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
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Size: 546816 |
Author: 黄奇家 |
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