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[Embeded-SCM Develop卷积码、CRC

Description: 卷积码的C源程序,包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6873 | Author: 潘华林 | Hits:

[Other resourcegongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6276 | Author: 李超 | Hits:

[Embeded-SCM Develop卷积码、CRC

Description: 卷积码的C源程序,包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6144 | Author: 潘华林 | Hits:

[VHDL-FPGA-Veriloggongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[Compress-Decompress algrithms601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[Special EffectscontourletC

Description: contourlet的C源程序,非常难找!contourlet是继小波后新出现的多尺度处理工具!-Contourlet the C source code, very difficult to find! After following the wavelet Contourlet emerging multi-scale processing tools!
Platform: | Size: 1903616 | Author: aclon | Hits:

[source in ebookRSencode

Description: 包含RS(10,8)的verilog源程序,加法器的verilog源程序,卷积码的verilog源程序-Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
Platform: | Size: 1024 | Author: bai | Hits:

[VHDL-FPGA-Verilogjuanjiqi

Description: 这是一个卷积器的设计,源码值得好好地学习-This is a convolution design, source code should be a good learning
Platform: | Size: 19456 | Author: lzc | Hits:

[VHDL-FPGA-VerilogConvolution

Description:
Platform: | Size: 104448 | Author: 龚阳 | Hits:

[Otherinterleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[Communicationconv_vhdl

Description: 用Verilog实现卷积码(2,1,2)的编码器,采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[VHDL-FPGA-Verilogjuanji

Description: 采用vhdl语言编写的卷积编码(2.1.7),通过调试可直接下载使用-Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging
Platform: | Size: 2048 | Author: wangminmin | Hits:

[VHDL-FPGA-VerilogVD-vhdl-Code

Description: this codes are for convolution encoder and Viterbi decoder synthesis and implementation.
Platform: | Size: 7168 | Author: shishir | Hits:

[VHDL-FPGA-Verilogconvolution

Description: convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
Platform: | Size: 152576 | Author: ant | Hits:

[VHDL-FPGA-Verilogconvol_enc

Description: VHDL code for convolution encoder for wimax PHY layer. This design also has control to add controlled amount of noise in encoded output.
Platform: | Size: 1024 | Author: zpatel | Hits:

[ActiveX/DCOM/ATLprepha_conj

Description: 本代码用VHDL实现了复数的卷积,也许对你会有用-this code written by VHDL completes the convolution of complex numbers,which may be quite helpful to you.
Platform: | Size: 1024 | Author: 王远路 | Hits:

[Otherviterbi_1

Description: low power convolution encoder and Viterbi decoder using vhdl code
Platform: | Size: 184320 | Author: Abhi | Hits:

[Embeded-SCM Develop卷积码、CRC

Description: 卷积码的C源程序,包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 7168 | Author: signific | Hits:

[VHDL-FPGA-VerilogJJ213_program

Description: 卷积码(213)的编译码,VHDL语言编写的整个工程文件,带有仿真结果图。-Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.
Platform: | Size: 301056 | Author: jz | Hits:

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