Search - vhdl random generator

[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] random data gen（vhdl）

Description: 任意数据发生器的源代码-arbitrary data source code generator
Platform: | Size: 97519 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] random data gen（vhdl）

Description: 任意数据发生器的源代码-arbitrary data source code generator
Platform: | Size: 97280 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[Other] TCNTL

Description: 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses
Platform: | Size: 634880 | Author: 张稀楠 | Hits:

[Other] prbs

Description: 伪随机序列产生器，VHDL程序，不记得在哪个论坛上下的。-Pseudo-random sequence generator, VHDL procedures, do not remember in which forum from top to bottom.
Platform: | Size: 2048 | Author: 韩丹 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilog] rng

Description: verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
Platform: | Size: 94208 | Author: Alex | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[Books] prbs

Description:
Platform: | Size: 166912 | Author: 5656 | Hits:

[Crack Hack] khalil2006_true_random_number_generator

Description: a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are required to generate public/private key pairs for asymmetric algorithm such as RSA and symmetric algorithm such as AES.
Platform: | Size: 418816 | Author: Hassan Abdelaziz | Hits:

[VHDL-FPGA-Verilog] pn127

Description: 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
Platform: | Size: 446464 | Author: lee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 8*8乘法器设计伪随机序列发生器 PS2键盘设计均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
Platform: | Size: 2048 | Author: qiumh | Hits:

[Mathimatics-Numerical algorithms] random

Description: 伪随机数产生器,可以根据输入的控制字产生需要的伪随机数-Pseudo-random number generator
Platform: | Size: 2048 | Author: chengaj | Hits:

[source in ebook] weisuiji

Description: 伪随机比特发生器， VHdL写的伪随机比特发生器-Pseudo-random bit generator, pseudo-random bit generator, VHdL written in pseudo-random bit generator,
Platform: | Size: 1024 | Author: 阿道夫 | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

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[Other resource] 一些VHDL源代码

[Other resource] random data gen（vhdl）

[VHDL-FPGA-Verilog] random data gen（vhdl）

[VHDL-FPGA-Verilog] 一些VHDL源代码

[Other] TCNTL

[Other] prbs

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] rng

[VHDL-FPGA-Verilog] fcsr

[Books] prbs

[Crack Hack] khalil2006_true_random_number_generator

[VHDL-FPGA-Verilog] pn127

[VHDL-FPGA-Verilog] VHDL

[Mathimatics-Numerical algorithms] random

[source in ebook] weisuiji

[Windows Develop] LFSR

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] VHDL-source-code

[Other] ZufallszahlengeneratorVHDL

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