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VHDL-FPGA-Verilog list
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UART interface verilog code, uart_tx、uart_rx, testbench
Update : 2025-01-16 Size : 192kb Publisher : lv

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WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
Update : 2025-01-16 Size : 410kb Publisher : lv

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Verilog implementarion of FSM. Solution for altera s lab 7 part2.
Update : 2025-01-16 Size : 10kb Publisher : iago

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Verilog FSM implementation for altera s lab(part 3 of lab 7).
Update : 2025-01-16 Size : 8kb Publisher : iago

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Verilog FSM implemetation for altera s lab 7(part IV) for de2115 fpga.
Update : 2025-01-16 Size : 9kb Publisher : iago

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FSM Verilog implementation of the final part of lab 7 of altera s verilog tutorial for de2115 fpga.
Update : 2025-01-16 Size : 9kb Publisher : iago

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Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each per
Update : 2025-01-16 Size : 7.97mb Publisher : 洪伟达

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fpga pmsm te
Update : 2025-01-16 Size : 28kb Publisher : 申彦磊

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7 segment counter in VHdl
Update : 2025-01-16 Size : 2.22mb Publisher : yassine

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This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards
Update : 2025-01-16 Size : 1kb Publisher : zhangpeng

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colorchecker VGA format standard color card production, can support any resolution settings
Update : 2025-01-16 Size : 1kb Publisher : 周召涛

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High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
Update : 2025-01-16 Size : 1.14mb Publisher : 周召涛
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