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realizaiton of timer16
Update : 2025-01-16 Size : 36kb Publisher : 朴巍

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Serial receive module code, according to the set baud rate, serial data can be correctly received
Update : 2025-01-16 Size : 1kb Publisher : Kevin

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tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk : in std_logic
Update : 2025-01-16 Size : 1kb Publisher : pablo

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programer for FPGA with spatan
Update : 2025-01-16 Size : 10kb Publisher : hiep

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1024 point fft FPGA hardware implementation
Update : 2025-01-16 Size : 55.9mb Publisher : 陈峰

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Altera series FPGA to achieve the VGA display 8 color images, debugging through, the development environment QuartusII, language verilog.
Update : 2025-01-16 Size : 6.56mb Publisher : PrudentMe

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Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.
Update : 2025-01-16 Size : 9.68mb Publisher : PrudentMe

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Use Altera PCIe IP core, supplement PCIe transaction layer, complete PCIe device side hardware design
Update : 2025-01-16 Size : 27.64mb Publisher : zhaodonglin

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DES encrypt verilog
Update : 2025-01-16 Size : 11kb Publisher : lv

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AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
Update : 2025-01-16 Size : 195kb Publisher : lv

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APB bus interface to I2C bus interface IP,verilog code
Update : 2025-01-16 Size : 434kb Publisher : lv

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Using Xilinx' s Virtex-5 chip lcd procedure
Update : 2025-01-16 Size : 300kb Publisher : zsd
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