VHDL-FPGA-Verilog List Page 4156

VHDL-FPGA-Verilog list

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bujindianjiVHDL Downloaded：0: positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
Update : 2025-01-11 Size : 5kb Publisher : 罗辉
sampleVHDL Downloaded：0: sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
Update : 2025-01-11 Size : 120kb Publisher : 罗辉
vhdl_clock Downloaded：0: VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparatio
Update : 2025-01-11 Size : 317kb Publisher : 赵海东
vhdl_traffic Downloaded：0: simulation experiment simulated traffic lights junction of red, yellow, and green traffic lights to the process of change, said LED lights for traffic lights, and the digital tube display the current state of the remaini
Update : 2025-01-11 Size : 195kb Publisher : 赵海东
vhdl_i2c Downloaded：0: 7. IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data switch E EPROM a certain address, pressed another button, just write the data back to reading CPLD,
Update : 2025-01-11 Size : 410kb Publisher : 赵海东
vhdl_dial Downloaded：0: dial-switch dial-switching experiment 8 0 1 state in seven of the eight corresponding digital control-show or a 0.
Update : 2025-01-11 Size : 158kb Publisher : 赵海东
vhdl_buzzer Downloaded：0: buzzer to buzzer this experiment certain frequency square wave can buzzer sounded a corresponding pitch. The experiment by designing a state machine and the buzzer sounded a divider so that the "multi-microphone to the s
Update : 2025-01-11 Size : 212kb Publisher : 赵海东
1_070116141639 Downloaded：0: verilog ps2 Programming Interface design, the design based fpga
Update : 2025-01-11 Size : 3kb Publisher : ykf
vhdl_led Downloaded：0: seven of the digital control experiments (including two experimental), the digital control of a Test : Dynamic scanning approach to the eight digital control "at the same time" show 0-7,
Update : 2025-01-11 Size : 356kb Publisher : 赵海东
VHDLnf Downloaded：0: VHDL arbitrary integer frequency,-- n as long as you want to set the frequency of the numerical breakdown on the
Update : 2025-01-11 Size : 1kb Publisher : 赵海东
1_061026140305 Downloaded：0: FPGA-based I2C bus simulation, using verilog HDL language.- Based on the FPGA I2C main line simulation, verilog uses the HDL language compilation.
Update : 2025-01-11 Size : 200kb Publisher :
chuanbingzhuanhuan Downloaded：0: VHDL code, through simulation, the variation can be downloaded into a document, but need to change, and change series
Update : 2025-01-11 Size : 3kb Publisher : 赵宾

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