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VHDL-FPGA-Verilog list
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a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.
Update : 2025-01-19 Size : 52kb Publisher : hj

Downloaded:0
a simple module to get the most of your on board heartbeat LED change or add more sequences easily in parameters file
Update : 2025-01-19 Size : 2kb Publisher : hj

Downloaded:0
convert VHDL files to Verilog files
Update : 2025-01-19 Size : 44kb Publisher : hj

Downloaded:0
FPGA digital signal processing (3rd Edition) verilog source
Update : 2025-01-19 Size : 557kb Publisher : 198996

Downloaded:0
VGA experiment, according to the requirements, dynamic display picture, dynamic picture of the effect of the screen is touched rebound
Update : 2025-01-19 Size : 9.9mb Publisher : 钱学森

Downloaded:0
Xilinx multi-core embedded system design form a complete set of CD source code
Update : 2025-01-19 Size : 19.83mb Publisher : 张鹏

Downloaded:0
A 5ppm INL and 5 V high speed 24 bit offset without delay increment accumulation (No Latency TM ADC LTC2440 delta sigma) source code
Update : 2025-01-19 Size : 1kb Publisher : 黄亚婷

Downloaded:0
Interface DDR2 read and write test module, ,test correctly
Update : 2025-01-19 Size : 111kb Publisher : 于工

FSK modulation and demodulation of VHDL program _ with _ test correctly
Update : 2025-01-19 Size : 1kb Publisher : 于工

Downloaded:0
The MASK VHDL program with _ _ modulation test
Update : 2025-01-19 Size : 1kb Publisher : 于工

MPSK modulation and demodulation of VHDL program _ with _ test correctly
Update : 2025-01-19 Size : 1kb Publisher : 于工

IQ signal generator _ with _ test correctly
Update : 2025-01-19 Size : 6kb Publisher : 于工
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