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VHDL-FPGA-Verilog list
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FPGAcode
Downloaded:0
Functions, tasks, finite state machine, the state machine interface design, SRAM FIFO design code implements
Update
: 2025-01-19
Size
: 8kb
Publisher
:
wxy
mux
Downloaded:0
verilog code it is about multiplexer
Update
: 2025-01-19
Size
: 102kb
Publisher
:
myank jaiswal
serial
Downloaded:0
This the function of test functions written in Verilog, mainly used in the test module, the program has been successful debugging.
Update
: 2025-01-19
Size
: 1kb
Publisher
:
尹框
vedio_format
Downloaded:1
this code describe the bt1120 generator and change form soure code.
Update
: 2025-01-19
Size
: 12.34mb
Publisher
:
kenzhu
VD_212_correction
Downloaded:0
Tian Yun and other book Wireless Communications FPGA design on page 324 of the code error has been corrected, and the code of the comments.At the same time gives the test bench files.
Update
: 2025-01-19
Size
: 239kb
Publisher
:
LIU-Jianlinag
fenpin5_5
Downloaded:0
the frequency of a rectangular wave is divided 5.5 using the FPGA
Update
: 2025-01-19
Size
: 340kb
Publisher
:
王斌一
master_bla
Downloaded:0
master bla altera quartus II version 15
Update
: 2025-01-19
Size
: 2kb
Publisher
:
wira
altdq_dqs2
Downloaded:0
altera ip a ltera ip
Update
: 2025-01-19
Size
: 2.15mb
Publisher
:
wira
alt_xaui
Downloaded:0
altera ip a ltera ip
Update
: 2025-01-19
Size
: 6.13mb
Publisher
:
wira
DTSM
Downloaded:0
In the development board can be achieved 00 to 59 counts, the equivalent of a 60 hexadecimal counter, which includes the pulse frequency of the code
Update
: 2025-01-19
Size
: 4kb
Publisher
:
张宇晴
descore_latest.tar
Downloaded:0
VHDL implementation of the classic DES block cipher (interactive architecture)
Update
: 2025-01-19
Size
: 6kb
Publisher
:
hj
pwm_latest.tar
Downloaded:0
pulse width modulator, work as one PWM or one timer. 16 bit main counter
Update
: 2025-01-19
Size
: 125kb
Publisher
:
hj
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444
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