VHDL-FPGA-Verilog List Page 445

VHDL-FPGA-Verilog list

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clock1 Downloaded：0: digital clock
Update : 2025-01-19 Size : 514kb Publisher : 瑞瑞
Top_MIL_1553B Downloaded：0: This the project, which implements MIL_1553 protocol.
Update : 2025-01-19 Size : 3kb Publisher : Alex
fpga Downloaded：0: When implemented in an FPGA multifunction digital clock, you can set the alarm, set the time.
Update : 2025-01-19 Size : 13.19mb Publisher : zhang
vga_1 Downloaded：0: DE2 Development and Education Board VGA display
Update : 2025-01-19 Size : 1.78mb Publisher :
Code-speed-adjustment-circuit Downloaded：0: Based on the synchronous digital multiplex system, namely the input data stream rate is the same. If the number of each branch, according to the code flow rate is not directly to pick up, because after the multiplex synt
Update : 2025-01-19 Size : 681kb Publisher : 谢政龙
kbd_uart Downloaded：0: The use of UART interface keyboard control circuit design based on FPGA, can realize some functions of keyboard control
Update : 2025-01-19 Size : 93kb Publisher : Hunter
PCIe_13.1 Downloaded：0: FPGA pcie13.0 interface control module download executable program based on direct control can achieve pcie13.0 interface
Update : 2025-01-19 Size : 648kb Publisher : Hunter
5CSXFC6D6F31C8N_pin_location Downloaded：0: Pin Terasic company SOC-KIT development board FPGA chip 5CSXFC6D6F31C8N distribution, and use this development board users
Update : 2025-01-19 Size : 490kb Publisher : Hunter
Borax_BA5_SoC_Kit_Rev2 Downloaded：0: Cytech technology Borax development board SoC_Kit examples of procedures for the development board users
Update : 2025-01-19 Size : 1.76mb Publisher : Hunter
ITU_656_Encoder Downloaded：0: The image programming code under the ITU_656 protocol, suitable for transmission of images to developers under this Agreement
Update : 2025-01-19 Size : 1kb Publisher : Hunter
CLK_DIV_IP_packager Downloaded：0: Examples of Vivado IP packager. Vivado version 2014.2, using the Verilog language for a division of the program package.
Update : 2025-01-19 Size : 674kb Publisher : LIU-Jianlinag
FPGAcode Downloaded：0: compare, division,half_clock,block and unblock
Update : 2025-01-19 Size : 4kb Publisher : wxy

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