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VHDL-FPGA-Verilog list
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Update : 2025-01-20 Size : 18.04mb Publisher : 张良

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Projet fréquencemetre réalisé en VHDL et implimenté sur la carte FPGA Cyclone
Update : 2025-01-20 Size : 1.16mb Publisher : Youssef

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DHL CLA20_20 development with the Verilog bit ahead carry adder code.
Update : 2025-01-20 Size : 365kb Publisher : 吴成芯

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compteur digital VHDL 1ERE VERSION
Update : 2025-01-20 Size : 2kb Publisher : hatim12

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The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode comma
Update : 2025-01-20 Size : 263kb Publisher : borhan

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uart loopback and test bench .
Update : 2025-01-20 Size : 6kb Publisher : borhan

fpga program for PWM inverter control, there are savers, including pulse lockout protection, notes, very easy to use
Update : 2025-01-20 Size : 2kb Publisher : 韩季晨

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FPGA-based realization of DDS signal generator can produce sine, square, ramp three waveforms.
Update : 2025-01-20 Size : 77kb Publisher : wangjiali

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Write Verilog FPGA-based SD card reader program, it is possible to read out the data stored in the SD card
Update : 2025-01-20 Size : 1.58mb Publisher : wangjiali

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FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
Update : 2025-01-20 Size : 2.71mb Publisher : wangjiali

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Using Verilog HDL language written on the realization of the ADC, MDC control procedures, personal use Quartus 7.2, in the above simulation carried out have had no problems found
Update : 2025-01-20 Size : 1kb Publisher : wangjiali

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ML605 LCD Verilog HDL prepared with flashing LED program, very simple
Update : 2025-01-20 Size : 2.01mb Publisher : wangjiali
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