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VHDL-FPGA-Verilog list
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SDR-SDRM
Downloaded:0
The project of Samsung SDR SDRAM (K4S641632), read and write, internal engineering points for PLL and reset processing module, SDRAM logic module, SDRAM logic module read SDRAM read and write encapsulation module, read a
Update
: 2025-01-22
Size
: 9.95mb
Publisher
:
陈超
VGA
Downloaded:0
VGA 640*480 controlling and blanking signal in Verilog HDL .
Update
: 2025-01-22
Size
: 2kb
Publisher
:
Dikshant Pandey
tlv5638_ise12migration
Downloaded:0
Using SPI communication protocol, quartusII development environment, the preparation of 5638 drivers
Update
: 2025-01-22
Size
: 483kb
Publisher
:
金英
tb_contrast_stretch
Downloaded:0
contrast strech for image pixles
Update
: 2025-01-22
Size
: 1kb
Publisher
:
Adnan
log_generator
Downloaded:0
log10 generator in vhdl. simulated in Modelsim
Update
: 2025-01-22
Size
: 3kb
Publisher
:
Adnan
wdog_sp805
Downloaded:0
The Watchdog module is an AMBA slave module and connects to the Advanced Peripheral Bus (APB). The Watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generat
Update
: 2025-01-22
Size
: 208kb
Publisher
:
st
calculator
Downloaded:0
Unsigned 8-bit multiplication and division can be achieved, simulation the written calculation proce
Update
: 2025-01-22
Size
: 1.12mb
Publisher
:
yujie
lcd_system
Downloaded:0
lcd system: Contains pictures show, Chinese character, lcd PS2 output display system.
Update
: 2025-01-22
Size
: 9.13mb
Publisher
:
刘佳益
FIFO
Downloaded:0
FIFO control the timing of urat, SDRAM, DAC and other timing understanding have helped
Update
: 2025-01-22
Size
: 6.27mb
Publisher
:
刘佳益
VHDL_Examples_DE1_SoC
Downloaded:0
DE1- COS learning routines, for FPGA with VHDL language display program written to buttons, helps to learn
Update
: 2025-01-22
Size
: 2.85mb
Publisher
:
刘国松
FIFO_Memory
Downloaded:0
FPGA memory implementation
Update
: 2025-01-22
Size
: 1.48mb
Publisher
:
Sandeep
DDR2-verilog
Downloaded:2
ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the FPGA and DDR2 communications.
Update
: 2025-01-22
Size
: 1.42mb
Publisher
:
wei
«
1
2
...
.14
.15
.16
.17
.18
519
.20
.21
.22
.23
.24
...
4311
»
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