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VHDL-FPGA-Verilog list
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The project of Samsung SDR SDRAM (K4S641632), read and write, internal engineering points for PLL and reset processing module, SDRAM logic module, SDRAM logic module read SDRAM read and write encapsulation module, read a
Update : 2025-01-22 Size : 9.95mb Publisher : 陈超

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VGA 640*480 controlling and blanking signal in Verilog HDL .
Update : 2025-01-22 Size : 2kb Publisher : Dikshant Pandey

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Using SPI communication protocol, quartusII development environment, the preparation of 5638 drivers
Update : 2025-01-22 Size : 483kb Publisher : 金英

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contrast strech for image pixles
Update : 2025-01-22 Size : 1kb Publisher : Adnan

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log10 generator in vhdl. simulated in Modelsim
Update : 2025-01-22 Size : 3kb Publisher : Adnan

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The Watchdog module is an AMBA slave module and connects to the Advanced Peripheral Bus (APB). The Watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generat
Update : 2025-01-22 Size : 208kb Publisher : st

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Unsigned 8-bit multiplication and division can be achieved, simulation the written calculation proce
Update : 2025-01-22 Size : 1.12mb Publisher : yujie

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lcd system: Contains pictures show, Chinese character, lcd PS2 output display system.
Update : 2025-01-22 Size : 9.13mb Publisher : 刘佳益

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FIFO control the timing of urat, SDRAM, DAC and other timing understanding have helped
Update : 2025-01-22 Size : 6.27mb Publisher : 刘佳益

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DE1- COS learning routines, for FPGA with VHDL language display program written to buttons, helps to learn
Update : 2025-01-22 Size : 2.85mb Publisher : 刘国松

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FPGA memory implementation
Update : 2025-01-22 Size : 1.48mb Publisher : Sandeep

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ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the FPGA and DDR2 communications.
Update : 2025-01-22 Size : 1.42mb Publisher : wei
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