VHDL-FPGA-Verilog List Page 530

VHDL-FPGA-Verilog list

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banjian Downloaded：0: Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.
Update : 2025-01-22 Size : 154kb Publisher : zwq
counter9 Downloaded：0: Design using VHDL input between minus a 0-9 counter, complete compilation, synthesis, simulation, test procedures, and gives the simulation waveforms
Update : 2025-01-22 Size : 183kb Publisher : zwq
max41a Downloaded：0: Schematic ways with 4-to-1 multiplexer, compile, synthesis, simulation testing and other steps
Update : 2025-01-22 Size : 171kb Publisher : zwq
5.4.5_LMS Downloaded：0: Automatic filter FPGA implementation using VHDL language!
Update : 2025-01-22 Size : 2.41mb Publisher : 廖阳阳
vending_machine Downloaded：0: Based on the FPGA development board NEXYS3 vending machine, and use the principle of VGA display on the LCD screen, using the keyboard to purchase and payment
Update : 2025-01-22 Size : 17.13mb Publisher : 黄志宇
stripe_mali Downloaded：0: This based on the FPGA development board NEXYS3 verilog program, is based on the principle of VGA screensaver, stripe and mobile super Mary
Update : 2025-01-22 Size : 1.62mb Publisher : 黄志宇
LFSR Downloaded：0: This based on the FPGA development board NEXTS3 a verilog program, is a linear feedback shift register LFSR, can be used to generate pseudo random Numbers
Update : 2025-01-22 Size : 839kb Publisher : 黄志宇
PS2_keyboard Downloaded：0: This based on the FPGA development board NEXYS3 a verilog program, is a ps2 keyboard module, including detection and decoding module
Update : 2025-01-22 Size : 604kb Publisher : 黄志宇
superdigitalclock Downloaded：0: This is based on the FPGA development board BASYS2 a intelligent digital clock, can divide three patterns: the minutes and seconds, of a second.Through the button switch mode and in digital tube display
Update : 2025-01-22 Size : 1.43mb Publisher : 黄志宇
10_CMOS_OV7725_RGB640480 Downloaded：0: Using FPGA EP4CE developed OV7725 camera video capture system, using Verilog realize
Update : 2025-01-22 Size : 751kb Publisher : leeyg
NiosII_I2C_bus Downloaded：0: Altera company EP3C using the Nios II series chip I2C bus-based design using Verilog coding
Update : 2025-01-22 Size : 12.89mb Publisher : leeyg
NiosII_SPI_bus Downloaded：0: Altera company EP3C using the Nios II series chip SPI bus-based design, using Verilog coding
Update : 2025-01-22 Size : 2.82mb Publisher : leeyg

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