Search - DMA vhdl

[Other resource] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 34569 | Author: xf | Hits:

[VHDL-FPGA-Verilog] pci 的vhdl 源代码

Description: pci 的vhdl 源代码-The source code of PCI VHDL.
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[VHDL-FPGA-Verilog] adma

Description: Wishbone dma ip core
Platform: | Size: 7168 | Author: liwen | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线，VHDL语言，硬件描述语言源码-SPI bus, VHDL language, hardware description language source code
Platform: | Size: 3072 | Author: 郑文棋 | Hits:

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3687424 | Author: hawd | Hits:

[VHDL-FPGA-Verilog] msp430_jtag_nios

Description: 将msp430与使用nios的fpga相连，将fpga作为msp430的jtag使用。其中用到了nios内的多种接口以及dma操作-The MSP430 with the use of the Nios FPGA connected to the FPGA as the MSP430 JTAG to use. Which used the Nios multiple interfaces and dma operation
Platform: | Size: 56320 | Author: danielmu | Hits:

[Other] mpdma.tar

Description: DMA VHDL 设计IP核经常遇到大数据交换要用DMA，本IP核来自开源组织，免费开源版-DMA VHDL design IP core often encountered in large data exchange to use DMA, the IP core from the open-source organizations, free open source version
Platform: | Size: 93184 | Author: | Hits:

[VHDL-FPGA-Verilog] DMA_Freeware

Description: 基于xilinx vierex5得pci express dma设计实现。-Based on a xilinx vierex5 realize pci express dma design.
Platform: | Size: 12781568 | Author: liu | Hits:

[Driver Develop] sg-dma

Description: DMA exmaple,网路上找到的DMA程式范例-DMA exmaple
Platform: | Size: 882688 | Author: 林家祥 | Hits:

[VHDL-FPGA-Verilog] datapath_fifo

Description: datapath_fifo used in DMA contect PCI in the DAB system the format of this file is VHDL
Platform: | Size: 1024 | Author: hjy | Hits:

[Communication-Mobile] wb_lpc_latest.tar

Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Platform: | Size: 410624 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] DMA_8237A

Description: 经典DMA控制器8237A的VHDL设计，对设计DMA控制器有很高的参考价值。-Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
Platform: | Size: 12288 | Author: neversee | Hits:

[VHDL-FPGA-Verilog] 8dma_bridge

Description: 基于Verilog hdl 的DMA控制代码-Verilog hdl-based control of the DMA code
Platform: | Size: 33792 | Author: wxd | Hits:

[VHDL-FPGA-Verilog] DMA

Description: 针对QUARTUS的DMA的VHDL代码实现-DMA Controller Code in VHDL
Platform: | Size: 2048 | Author: hejian | Hits:

[VHDL-FPGA-Verilog] CPU_Architecture

Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Platform: | Size: 2388992 | Author: Amit Adoni | Hits:

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[Other resource] SRAM@DMA实验

[VHDL-FPGA-Verilog] pci 的vhdl 源代码

[VHDL-FPGA-Verilog] SRAM@DMA实验

[VHDL-FPGA-Verilog] adma

[VHDL-FPGA-Verilog] spi

[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26

[VHDL-FPGA-Verilog] msp430_jtag_nios

[Other] mpdma.tar

[VHDL-FPGA-Verilog] DMA_Freeware

[Driver Develop] sg-dma

[VHDL-FPGA-Verilog] datapath_fifo

[Communication-Mobile] wb_lpc_latest.tar

[VHDL-FPGA-Verilog] DMA_8237A

[VHDL-FPGA-Verilog] 8dma_bridge

[VHDL-FPGA-Verilog] DMA

[VHDL-FPGA-Verilog] CPU_Architecture

[Graph program] wb_dma

[VHDL-FPGA-Verilog] AlteraDMAdetector

[VHDL-FPGA-Verilog] dma_hussam

[VHDL-FPGA-Verilog] DMA

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