Search - FPGA UART Verilog

[VHDL-FPGA-Verilog] uart_verilog

Description: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Platform: | Size: 9216 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] Altera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[Other] PCI_Bridge_Guest_UART

Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Platform: | Size: 8427520 | Author: heartbeat | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: 简化的串口通信，去掉了奇偶校验位，波特率为9600，测试通过，fpga型号为xinlinx vp20-Simplified serial communication, removing the parity bit, the baud rate to 9600, test, fpga model xinlinx vp20
Platform: | Size: 5120 | Author: 刘红亮 | Hits:

[VHDL-FPGA-Verilog] uartsourcecode

Description: uart的FPGA模块，基于VHDL、verilog语言-the FPGA UART modules, based on VHDL, verilog language
Platform: | Size: 293888 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] uart

Description:
Platform: | Size: 14336 | Author: 顾向南 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[Com Port] uart

Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
Platform: | Size: 3072 | Author: 赵云 | Hits:

[Other Embeded program] uart

Description: fpga 串行口接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
Platform: | Size: 371712 | Author: james | Hits:

[Com Port] UART

Description: 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the procedures and instructions, validate through, with good stability and reference value!
Platform: | Size: 2269184 | Author: Kerwin | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[Com Port] FPGA-RS232-verilog

Description: fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug debugging assistant
Platform: | Size: 500736 | Author: yvaine | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

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[VHDL-FPGA-Verilog] uart_verilog

[VHDL-FPGA-Verilog] Altera_uart_Verilog

[VHDL-FPGA-Verilog] u-uart

[Other] PCI_Bridge_Guest_UART

[VHDL-FPGA-Verilog] uart_verilog

[VHDL-FPGA-Verilog] uartsourcecode

[VHDL-FPGA-Verilog] Fusion_UART

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] UART

[Industry research] UART_DESIGN

[Com Port] uart

[Other Embeded program] uart

[Com Port] UART

[Other] uart_rx

[Com Port] FPGA-RS232-verilog

[VHDL-FPGA-Verilog] FPGA_UART

[VHDL-FPGA-Verilog] Uart

[VHDL-FPGA-Verilog] uart

[Other] FPAG UART Verilog

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