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[VHDL-FPGA-Verilog] 八位的伪随机数产生的verilog文件

Description: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback- shift-register
Platform: | Size: 2048 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] 双路脉冲发生器（veralog）

Description: Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is written I hope to help you, it can be mail : shaojunwu1@163.com
Platform: | Size: 4096 | Author: 邵君武 | Hits:

[VHDL-FPGA-Verilog] xljcq

Description: 关于序列发生器的verilog. 希望能帮大家。-sequence generator on the Verilog. Hope you can help.
Platform: | Size: 3072 | Author: 曹杨 | Hits:

[VHDL-FPGA-Verilog] wavegenerator_testbench

Description: 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
Platform: | Size: 4096 | Author: liu | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Platform: | Size: 784384 | Author: 东子 | Hits:

[VHDL-FPGA-Verilog] 9.1_ONE_PULSE

Description: 基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 　　9.1.1 由系统功能描述时序关系 　　9.1.2 流程图的设计 　　9.1.3 系统功能描述 　　9.1.4 逻辑框图 　　9.1.5 延时模块的详细描述及仿真 　　9.1.6 功能模块Verilog-HDL描述的模块化方法 　　9.1.7 输入检测模块的详细描述及仿真 　　9.1.8 计数模块的详细描述 　　9.1.9 可编程单脉冲发生器的系统仿真 　　9.1.10 可编程单脉冲发生器的硬件实现 　　9.1.11 关于电路设计中常用的几个有关名词 -based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Description logic diagram 9.1.5 9.1.4 Delay Module detailed description and simulation of 9.1. 6 functional modules Verilog-HDL description of the modular input method detection module 9.1.7 detailed 9.1.8 Description and Simulation module counting a detailed description 9.1.9 programmable pulse generator system 9.1.10 Simulation programmable pulse generator hardware on the circuit design 9.1.11 Constant Some of the terminology
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] 9.2_LCD_PULSE

Description: 基于Verilog-HDL的硬件电路的实现 9.2 具有LCD显示单元的可编程单脉冲发生器 　　9.2.1 LCD显示单元的工作原理 　　9.2.2 显示逻辑设计的思路与流程 　　9.2.3 LCD显示单元的硬件实现 　　9.2.4 可编程单脉冲数据的BCD码化 　　9.2.5 task的使用方法 　　9.2.6 for循环语句的使用方法 　　9.2.7 二进制数转换BCD码的硬件实现 　　9.2.8 可编程单脉冲发生器与显示单元的接口 　　9.2.9 具有LCD显示单元的可编程单脉冲发生器的硬件实现 　　9.2.10 编译指令-"文件包含"处理的使用方法 -based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardware 9.2.4 programmable single pulse data BCD of the task 9.2.5 9.2.6 for the use of the phrase cycle use 9.2.7 binary conversion of BCD programmable hardware 9.2.8 single pulse generator with a said unit 9.2.9 interface with the LCD display module programmable pulse generator hardware 9 .2.10 compiler directives- "document includes" the use of
Platform: | Size: 5120 | Author: 宁宁 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[VHDL-FPGA-Verilog] vga_gen_46

Description: Verilog Vga Generator -Verilog Vga Generator
Platform: | Size: 1024 | Author: Fermat | Hits:

[VHDL-FPGA-Verilog] sin

Description: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Platform: | Size: 2529280 | Author: 112254 | Hits:

[VHDL-FPGA-Verilog] single

Description: verilog 我自己写得按单脉冲发生器，通过了综合和仿真，和频率可变的正弦波发生器，-verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,
Platform: | Size: 1024 | Author: 潘见 | Hits:

[Other Embeded program] dds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
Platform: | Size: 4096 | Author: 白天 | Hits:

[VHDL-FPGA-Verilog] rng

Description: verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
Platform: | Size: 94208 | Author: Alex | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[Other] rng_opencore

Description: opencore, random number generator, verilog
Platform: | Size: 3072 | Author: jason | Hits:

[VHDL-FPGA-Verilog] VGADIY

Description: 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
Platform: | Size: 416768 | Author: mcuxxq | Hits:

[Crack Hack] lfsr

Description: 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] ffcsr

Description: 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 2048 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: Viterbi verilog generator
Platform: | Size: 81920 | Author: zhanglh | Hits:
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