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[Communication] DDS_VERILOG

Description: 本例给出了DDS的VERIOG的程序事例,可发生正弦\余弦等波形,适应与通信方面的硬件实现!-the cases presented DDS VERIOG procedures example, can occur sine \ cosine wave such as, Adaptation and communications hardware realization!
Platform: | Size: 3072 | Author: 陈榧 | Hits:

[Windows CE] DDSFPGA_cylone

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
Platform: | Size: 637952 | Author: 苏纳 | Hits:

[SCM] DDS+51

Description: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Platform: | Size: 1027072 | Author: 吴健 | Hits:

[SCM] FPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Platform: | Size: 1371136 | Author: haoren | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[VHDL-FPGA-Verilog] dds_using_FPGA

Description: verilog编写基于fpga的DDS实现-Verilog prepared based on the FPGA to achieve the DDS
Platform: | Size: 448512 | Author: 宇天 | Hits:

[SCM] Verilog

Description: DDS，FPGA产生，用verilog语言实现-DDS, FPGA generated using Verilog language
Platform: | Size: 25600 | Author: | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[VHDL-FPGA-Verilog] AM

Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Platform: | Size: 1687552 | Author: baixiangzhou | Hits:

[SCM] dds

Description: 关于FPGA中DDS核参数设置的资料，英文版的XILINX资料-DDS on the FPGA in the data set of nuclear parameters, the English version of XILINX information
Platform: | Size: 1664000 | Author: 李晶 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[SCM] dds

Description: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序-ewfreytrgrwf reggwrter rgterthhrgdfs rgdgf egrthg rgreaf rtgerf srfefsf frafgsf frghrsrgwgt
Platform: | Size: 28672 | Author: nbonwenli | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于Verilog的dds设计，已经经过调试，可直接使用-Dds of Verilog-based design, has been testing can be used directly
Platform: | Size: 2041856 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA控制AD9854的源文件，verilog，附有简单文档。-FPGA to control the AD9854 source file, verilog, with a simple document.
Platform: | Size: 820224 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] FPGA-DDS

Description: 在FPGA内，以查表方式实现频率直接合成器（DDS）功能。verilog源代码-In the FPGA in order to achieve the look-up table means the direct synthesizer frequency (DDS) feature. verilog source code
Platform: | Size: 2048 | Author: niuqs | Hits:

[VHDL-FPGA-Verilog] DDSVerilog

Description: DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation
Platform: | Size: 71680 | Author: caixiang | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 同时用verilog 语言编写dds原代码用于生成正余弦波，并在FPGA平台进行验证-described dds direct digital frequency synthesis of the basic tenets addition to the use of verilog prepared dds source used to produce sine, and FPGA development platform for verification
Platform: | Size: 1024 | Author: scond | Hits:

[VHDL-FPGA-Verilog] DDS-in-Verilog

Description: Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
Platform: | Size: 464896 | Author: haby | Hits:

[VHDL-FPGA-Verilog] dds(1)

Description: 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
Platform: | Size: 11024384 | Author: 电磁驱动 | Hits:

[Other] DDS

Description: DDS FPGA Verilog vhdl
Platform: | Size: 180224 | Author: 雨留兰 | Hits:
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