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[VHDL-FPGA-Verilog] vhdl_clock

Description: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。 以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 324608 | Author: 赵海东 | Hits:

[Other] C2

Description: 功能更加完善的基于vhdl的数字时钟设计 有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定 、、、、、、、 秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared.
Platform: | Size: 817152 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这是一个实现时分秒的时钟功能的源码，采用vhdl语言编写，已写好led驱动，可直接在数码管上显示-Realize this is an accurate clock function when the source code, the use of VHDL language has been written led drive directly in the digital tube display
Platform: | Size: 246784 | Author: xiaoshuai | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Platform: | Size: 1339392 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] clock_design

Description: 数字钟的verilog代码，quartusII开发环境.-Digital Clock in Verilog code, quartusII development environment.
Platform: | Size: 414720 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog] txxclock

Description: VHDL编写的数字钟，在Q-ii下编译，实现闹铃设置与定时闹铃，分时秒显示-VHDL prepared digital clock, in the Q-ii under the compiler to achieve regular alarm and alarm settings, time-seconds display
Platform: | Size: 308224 | Author: | Hits:

[VHDL-FPGA-Verilog] ssz

Description: 数字钟，用VHDL写的各个模块，顶层用图形编辑，在实验箱上完全通过-Digital clock, using VHDL written by various modules, top-level graphics editing, in the experimental box completely through
Platform: | Size: 257024 | Author: kevin liu | Hits:

[assembly language] 1234

Description: 多功能数字钟，、在quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -Multifunction digital clock, in the quartus 2 compiler environment through 4, simulation through and get the correct waveform 5, gives the design report
Platform: | Size: 1187840 | Author: 陈飞 | Hits:

[assembly language] clock

Description: 电子课程设计数字钟的源代码，已在试验箱上实现，定义了管脚。可以调整时间-E-curriculum design digital clock source code has been achieved in the chamber, the definition of a pin. Can adjust the time
Platform: | Size: 501760 | Author: 龙龙 | Hits:

[Other] sheji2

Description: 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applications.
Platform: | Size: 131072 | Author: 周妮 | Hits:

[Other] clock

Description: 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clock functions. Minimum resolution of 1 second.
Platform: | Size: 680960 | Author: cindy | Hits:

[VHDL-FPGA-Verilog] digital_clock_design

Description: 利用VHDL语言，逻辑器件设计CPLD，实现数字钟-Using VHDL language, design of logic devices CPLD, digital clock
Platform: | Size: 634880 | Author: fei | Hits:

[VHDL-FPGA-Verilog] shuizhongvhdl

Description: 这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design
Platform: | Size: 1024 | Author: 小黄 | Hits:

[VHDL-FPGA-Verilog] digitalwatch

Description: Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes-Describe: This is VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Platform: | Size: 92160 | Author: eric carmen | Hits:

[VHDL-FPGA-Verilog] SZZ

Description: 这是一个数字钟的VHDL语言，具有调时、调秒、调分功能，同时，还具有十二小时制向二十四小时制切换功能-This is a digital clock in VHDL language, with a tune, the tone seconds and sub-transfer function, while the system also has 12 hours to 24 hours the system switching function
Platform: | Size: 851968 | Author: 蔡斌 | Hits:

[VHDL-FPGA-Verilog] vsz

Description: 这是一段数字钟的VHDL程序，简单易行。具有闹钟功能 ，适用于初学者。-This is a digital clock in VHDL process, simple and easy. With the alarm clock function, for beginners.
Platform: | Size: 57344 | Author: 星光 | Hits:

[Windows Develop] 0608190248xiatao

Description: 实验利借助于Quartus II 软件设计了一个多功能数字钟，实现了校时，校分，清零，保持和整点报时等多种基本功能，此外还实现了闹钟，星期，音乐闹铃等附加功能。本文首先利用Quartus II进行原理图设计并仿真调试，最后在实验板上验证了设计的正确性。 关键字：数字钟 闹钟 仿真 准点报时 -Quartus II software by means of experimental Lee designed a multi-functional digital clock and realized the school, the school hours, cleared, and the whole point of time keeping and other basic functions, in addition to achieve the alarm clock, week, music, alarm, etc. Additional function. This paper carried out using Quartus II schematic design and simulation debugging, and finally verified in the experimental board design is correct. Keywords: digital clock alarm clock simulation of quasi-point of time
Platform: | Size: 1185792 | Author: 李敬超 | Hits:

[VHDL-FPGA-Verilog] clock

Description: digital clock in VHDL.
Platform: | Size: 4096 | Author: dan | Hits:

[VHDL-FPGA-Verilog] digital-clock-in-vhdl

Description: digital clock display
Platform: | Size: 48128 | Author: nitish | Hits:
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