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[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[MiddleWare] code

Description: 数字锁相环的源代码。用硬件编程语言VHDL编写。-Digital phase-locked loop
Platform: | Size: 2048 | Author: zaoyexu | Hits:

[Other] 02

Description: 基于VHDL的全数字锁相环的设计 有关键部分的源代码 hehe !-VHDL-based all-digital phase-locked loop has a key part of the design of the source code hehe!
Platform: | Size: 167936 | Author: zhou wan | Hits:

[Other] clkrecoveryDPLL

Description: 用于时钟恢复的全数字锁相环设计，可以去掉时钟的抖动。-Clock recovery for all-digital phase-locked loop design, the clock jitter can be removed.
Platform: | Size: 1024 | Author: BrivaMa | Hits:

[Software Engineering] pllddfs

Description: 一种基于锁相环的数字频率合成器的设计-Based on Phase-Locked Loop Digital Frequency Synthesizer Design
Platform: | Size: 111616 | Author: 周真 | Hits:

[Software Engineering] SW

Description: FPGA弹弓无线呼叫系统分发射和接收两大部分。发射部分采用锁相环式频率合成器技术-FPGA slingshot wireless call system transmitting and receiving at most two. Part of the launch phase-locked loop frequency synthesizer using technology
Platform: | Size: 628736 | Author: w | Hits:

[VHDL-FPGA-Verilog] weifenqi

Description: 微分器：利用数字锁相环进行位同步信号提取的关键模块-Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules
Platform: | Size: 125952 | Author: 邓代竹 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ-FPGA realization of all-digital phase-locked loop, using hardware description Convocation verilog HDL, the top-level document DPLL. V
Platform: | Size: 4096 | Author: YP | Hits:

[Other] pll1

Description: 该程序实现的功能是数字锁相环的设计。源代码可以直接进行仿真试验◎-The program s function is to achieve the design of digital phase-locked loop. Source code can be directly carried out simulation test ◎
Platform: | Size: 1024 | Author: 苗黄 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.
Platform: | Size: 2854912 | Author: lijingfeng | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
Platform: | Size: 178176 | Author: 冯勇 | Hits:

[VHDL-FPGA-Verilog] FPGA-DPLL

Description: 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
Platform: | Size: 181248 | Author: lixu | Hits:

[VHDL-FPGA-Verilog] pll

Description: 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Platform: | Size: 10079232 | Author: gk | Hits:

[VHDL-FPGA-Verilog] newDPLLdesign

Description: 使用VHDL语言进行数字锁相环的设计，pdf格式，可以打开-The use of VHDL language design of digital phase-locked loop, pdf format, you can open
Platform: | Size: 557056 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] NewWayOfDPLLdesign

Description: 使用VHDL语言进行设计DPLL（数字锁相环）的相关文件-The use of VHDL language design DPLL (digital phase-locked loop) of the relevant documents
Platform: | Size: 223232 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] DPLL2

Description: 全数字锁相环电路的研制，使用的是VHDL语言 -All-digital phase-locked loop circuit development, using the VHDL language
Platform: | Size: 216064 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Communication-Mobile] pll

Description: 实现同步时采用锁相环，锁相环实现的原理，及源代码，-Implementation of the principle of phase-locked loop, and the source code,
Platform: | Size: 111616 | Author: qin | Hits:

[VHDL-FPGA-Verilog] shuzisuoxiang

Description: 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of applications. With the traditional analog circuit implementation of the PLL in comparison, DPLL with high accuracy, free from the impact of temperature and voltage, loop bandwidth and center frequency adjustable programming, easy to build a high-order phase-locked loop, etc..
Platform: | Size: 1024 | Author: hellen | Hits:
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