Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated Platform: |
Size: 5120 |
Author:王刚 |
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Description: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform Platform: |
Size: 675840 |
Author:zzwuyu |
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Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input. Platform: |
Size: 98304 |
Author:宫逢源 |
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Description: 基于ROM的正弦波发生器的设计:使用MATLAB得到这64个波形数据，将这些存数据写入一个ROM中。再输入时钟，每个上升沿依次读取一个波形数据-ROM-based sine wave generator of the design: the use of MATLAB to obtain waveform data 64, to write the data in a ROM. Re-enter the clock, each rising edge followed by a read waveform data Platform: |
Size: 101376 |
Author:evelyn |
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Description: 用LPM_ROM设计存放一个周期的256×8大小的rom,构建简易频率可控的正弦波发生器。
-LPM_ROM design store with a cycle of 256 × 8 size of rom, build a simple sine wave generator frequency controllable. Platform: |
Size: 122880 |
Author:张炳良 |
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Description: 基于EPM7128的数字合成信号发生器（DDS）设计。通过对EPM7128编程，组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized Platform: |
Size: 354304 |
Author:xiaoyu |
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Description: 该资料介绍了用FPGA实现正弦波发生器，原理是利用内置rom表，通过查询的方式实现输出，然后经过外部DAC输出，频率达到1MHz-The information on the sine wave generator using FPGA implementation, the principle is the use of built-in rom form, by querying the means to achieve the output, and then an external DAC output frequency of 1MHz Platform: |
Size: 2190336 |
Author:陈振林 |
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Description: 基于ROM的正弦波发生器的设计
一．实验目的
1. 学习VHDL的综合设计应用
2. 学习基于ROM的正弦波发生器的设计
二．实验内容
设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based sine wave generator design
1. Purpose of the experiment
1. VHDL Integrated Design and Application of Learning
2. Learning ROM-based sine wave generator design
2. Experimental content
ROM-based sine wave generator design, its compilation, simulation.
Specific requirements:
1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules
Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB.
3. The 50MHz input clock. Platform: |
Size: 17408 |
Author:爱好 |
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Description: 信号发生器是一种常用的仪器，能够实现各种波形，不同频率的输出，电子测试系统的重要部件。本研究
的数字信号发生器足基于直接数字合成即DDS技术设计的，采用VHDL与C语言相结合的方法，通过查找存储
于ROM查找表中的各种标准波形数据，产牛频率Hf调并且高精度的正弦波、方波、锯齿波等常用信号，并且町
以通过修改表中的数据，实现任意信号发生器-Signal generator is a commonly used instrument to achieve a variety of waveforms of different frequency output, a key component of electronic test systems. In this study, full digital signal generator that is based on DDS technology of direct digital synthesis design, VHDL and C language using the method of combining, by looking up stored in ROM look-up table in a variety of standard waveform data, the cattle and the high frequency tone Hf accuracy of the sine wave, square wave, sawtooth and other signals used, and town to modify table data, an arbitrary signal generator Platform: |
Size: 268288 |
Author:姚木 |
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Description: 在本设计中，时钟信号通过分频计产生一个理想的目标时钟频率，控制地址发生器计数，地址发生器的计数结果输出给正弦波数据存数ROM，作为其地址，从该地址取出ROM里的存储好的数据，再通过DA转换，将数字信号转换成模拟信号，最后输出给示波器观察。-In this design, the clock signal generated by frequency meter an ideal target clock frequency, the control address generator counts, count result output address generator to keep the number of sine wave data in ROM, as its address, remove the ROM from the address where good data storage, and then through the DA converter, the digital signal into an analog signal, the final output to the oscilloscope. Platform: |
Size: 2502656 |
Author:刘睿阳 |
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Description: vhdl语言正弦信号发生器设计，传统的用分立元件或通用数字电路元件设计电子线路的方法设计周期长,花费大,
可移植性差。本文以正弦波发生器为例,利用EDA 技术设计电路,侧重叙述了用VHDL 来完
成直接数字合成器(DDS) 的设计,DDS 由相位累加器和正弦ROM 查找表两个功能块组成,其
中ROM查找表由兆功能模块LPM-ROM来实现。-The traditional use of discrete components or general purpose digital circuit design method of electronic circuit design cycle is long, expensive, poor portability. In this paper, sine wave generator, for example, circuit design using EDA technology, focusing on the use of VHDL description to complete the direct digital synthesizer (DDS) design, DDS ROM from the phase accumulator and sine lookup table composed of two functional blocks, including ROM lookup table by the LPM-ROM modules trillion to implement. Platform: |
Size: 94208 |
Author:枫蓝 |
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Description: 设计一个正弦信号发生器，使用凌阳公司的16位单片机SPCE061A作为中央控制器，结合DDS芯片AD9850，产生0～15MHz频率可调的正弦信号,正弦信号频率设定值可断电保存；使用宽频放大技术，在50Ω负载电阻上使1K～10MHz范围内的正弦信号输出电压幅度VP-P=6V±1V；产生载波频率可设定的FM和AM信号；调制信号为1KHz的正弦波，调制信号的产生采用DDS技术，由CPLD和Flash ROM加上DAC进行直接数字合成；二进制基带序列码由CPLD产生，在100KHz固定载波频率下进行数字键控，产生ASK，PSK信号。-Design of a sinusoidal signal generator, the use of Sunplus 16-bit MCU SPCE061A as the central controller, combined with DDS chip AD9850, have adjustable frequencies 0 ~ 15MHz sinusoidal signal, sinusoidal signal frequency settings can be stored power using broadband amplification, in a 50Ω load resistor to 1K ~ 10MHz sinusoidal signal within the output voltage amplitude VP-P = 6V ± 1V generating the carrier frequency of the FM and AM can be set signal 1KHz sine wave modulation signal, modulated signal generation using DDS technology, coupled by the CPLD and Flash ROM DAC for direct digital synthesis binary baseband sequence code generated by the CPLD in a fixed carrier frequency 100KHz digital keying, resulting in ASK, PSK signals. Platform: |
Size: 29696 |
Author:王金 |
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Description: 设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。-ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch module 2 waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64 point sine wave data, waveform data obtained using MATLAB. 3 to 50MHz clock as input. Platform: |
Size: 65536 |
Author:坐听晚风赏晚霞 |
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Description: VHDL设计的相关实验，包括4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现。-VHDL design of experiments, including four reversible counters, four reversible binary code- Gray code converter design, the sequence detector design, the ROM-based sine wave generator design, digital lock design and implementation. Platform: |
Size: 49152 |
Author:张联合 |
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Description: 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能，且数据ROM 在高速条件下，占用最少的逻辑资源，设计流程最便捷，波形数据获最方便。下图是此信号发生器结构图，顶层文件SINGT.VHD 在FPGA 中实现，包含2 个部分：ROM 的地址信号发生器，由5 位计数器担任，和正弦数据ROM，拒此，ROM由LPM_ROM模块构成能达到最优设计，LPM_ROM底层是FPGA中的EAB或ESB等。地址发生器的时钟CLK的输入频率f0与每周期的波形数据点数（在此选择64 点），以及D/A输出的频率f 的关系是：f=f0/64。-Sinusoidal signal generator design, the structure of the sinusoidal signal generator consists of three parts. The data counter, or address generator, data ROM and D/A. The good performance of the sinusoidal signal generator design requirements Part 3 high-speed performance, and the ROM data in high-speed conditions, take up minimal logic resources, the design process is the most convenient, the waveform data is the most convenient. The following figure is a block diagram of this signal generator, top file SINGT.VHD is implemented in FPGA, consists of two parts: ROM address signal generator, served by the 5-bit counter, and the sine ROM reject this ROM by LPM_ROM module constitute optimal design LPM_ROM is the underlying FPGA EAB or ESB. The address generator clock CLK input frequency f0 and per period of the waveform data points selected in (64), and the relationship between D/A output frequency f is: f = f0/64. Platform: |
Size: 1825792 |
Author:吴祥 |
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