Search - wave generator vhdl

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[Other] wave

Description: 波形发生器的vhdl源代码，6个通道同步-Waveform generator of the VHDL source code, six-channel synchronization
Platform: | Size: 1024 | Author: gcy | Hits:

[VHDL-FPGA-Verilog] sinewave

Description: 6通道正弦波发生器，产生频率，相位，幅值都可调的正弦波形-6-channel sine wave generator, resulting in frequency, phase, amplitude of the sinusoidal waveform are adjustable
Platform: | Size: 1024 | Author: 桑武斌 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[VHDL-FPGA-Verilog] sin_generator

Description: 在quartus 11 5.1 里用VHDL编写的正弦波发生器，经过仿真通过-Quartus 11 5.1 years in VHDL prepared using sine wave generator, through simulation through
Platform: | Size: 245760 | Author: 郭翠双 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D159

Description: 正弦波发生器,VHDL的应用和处理,可以产生任意波形-Sine wave generator, VHDL applications and processing, can generate arbitrary waveform
Platform: | Size: 1731584 | Author: WBT | Hits:

[SCM] wave-generator

Description: 产生方波，三角波，正弦波，余弦波等波形，并且可以自由选择和切换，最后可以用于波形输出-Have a square wave, triangle wave, sine wave, cosine wave, such as waveform, and can freely choose and switch, and finally can be used for waveform output
Platform: | Size: 6144 | Author: 周易 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[Other] bxfsq

Description: 波形发生器的代码，具有产生正弦波、方波、三角波的功能。-Waveform Generator code has generated sine wave, square, triangle-wave function.
Platform: | Size: 16384 | Author: 李仁刚 | Hits:

[SCM] signal

Description: verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
Platform: | Size: 5519360 | Author: ray | Hits:

[VHDL-FPGA-Verilog] sine_wave_generator_using_FPGA_implementation

Description: 该资料介绍了用FPGA实现正弦波发生器，原理是利用内置rom表，通过查询的方式实现输出，然后经过外部DAC输出，频率达到1MHz-The information on the sine wave generator using FPGA implementation, the principle is the use of built-in rom form, by querying the means to achieve the output, and then an external DAC output frequency of 1MHz
Platform: | Size: 2190336 | Author: 陈振林 | Hits:

[VHDL-FPGA-Verilog] wave

Description: 可控脉冲发生器的VHDL源代码。设计文件加载到目标器件后，按下按键开关模块的S8按键，在输出观测模块通过示波器可能观测到一个频率约为1KHZ、占空比为50 的矩形波。按下S1键或者S2键，这个矩形波的频率会发生相应的增加或者减少。按下S3键或者S4键，这个矩形波的占空比会相应的增加或减少。-Controllable pulse generator of the VHDL source code. Design documents loaded to the target device and press the button switch module, S8 keys in the output observation module may be observed through the oscilloscope to a frequency of approximately 1KHZ, 50 duty cycle rectangular wave. Press the S1 key or S2 key, the frequency of this rectangular wave occurs a corresponding increase or decrease. Press the S3 or S4 key key, the rectangular wave duty cycle will be a corresponding increase or decrease.
Platform: | Size: 1024 | Author: 王唐小菲 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] wave-generator(vhdL0

Description: 10章波形信号发生器 vhdl波形发生器很有学习价值-Waveform signal generator VHDL is learning value waveform generator
Platform: | Size: 52224 | Author: wlb | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-sine-wave-generator

Description: it is a simple code in vhdl for sine wave generator. the test bench code is also provided in ths code
Platform: | Size: 21504 | Author: nasimus | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 正弦波发生器代码VHDL 其中包括分频正弦波数据-Sine wave generator VHDL code Divide the sine wave data including
Platform: | Size: 7168 | Author: 123456789 | Hits:

[VHDL-FPGA-Verilog] Signal-Generator-VHDL-design

Description: 信号发生器VHDL设计波形可选：正弦(sine)，方波(sqr)，锯齿波(jc_de和jc_in两种)，三角波(sanj)和阶梯波(stair)信号模块-Optional waveform signal generator VHDL design: sinusoidal (sine), square wave (sqr), sawtooth (jc_de and jc_in two kinds), triangle wave (sanj) and staircase (stair) signal modules
Platform: | Size: 758784 | Author: | Hits:

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[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

[VHDL-FPGA-Verilog] 8bitsine

[Other] wave

[VHDL-FPGA-Verilog] sinewave

[assembly language] sine

[VHDL-FPGA-Verilog] sin_generator

[VHDL-FPGA-Verilog] 61EDA_D159

[SCM] wave-generator

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] VHDL-ROM4

[Other] bxfsq

[SCM] signal

[VHDL-FPGA-Verilog] sine_wave_generator_using_FPGA_implementation

[VHDL-FPGA-Verilog] wave

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] wave-generator(vhdL0

[VHDL-FPGA-Verilog] vhdl-code-for-sine-wave-generator

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] Signal-Generator-VHDL-design

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