Search - sine wave using vhdl

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] DDS234

Description: 文中给出了用VHDL实现三角波正弦波方波的代码, 可以在maxPLUX2上运行,-In this paper, using the VHDL-wave sine wave square wave triangle realize the code, you can run maxPLUX2,
Platform: | Size: 2048 | Author: qibinchuan | Hits:

[VHDL-FPGA-Verilog] box

Description: 用vhdl语言编写的基于fpga的波形发生器，使用了quartusII程序。可以在1602液晶显示器上显示目前的波形种类。产生的波形分别是正弦波，三角波，锯齿波和方波。-VHDL language using FPGA-based waveform generator, using the procedures quartusII. 1602 liquid crystal display can show the current waveform types. Generated waveforms are sine wave, triangle wave, sawtooth and square wave.
Platform: | Size: 1708032 | Author: zhg | Hits:

[VHDL-FPGA-Verilog] sin_generator

Description: 在quartus 11 5.1 里用VHDL编写的正弦波发生器，经过仿真通过-Quartus 11 5.1 years in VHDL prepared using sine wave generator, through simulation through
Platform: | Size: 245760 | Author: 郭翠双 | Hits:

[VHDL-FPGA-Verilog] DDS-320-modu

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。-320x240 screen using the design of experiments to run me generate sine wave, AM FM waveforms, sweep.
Platform: | Size: 1250304 | Author: hangyinli | Hits:

[VHDL-FPGA-Verilog] sine

Description: chdl 64位计数器，利用mif格式文件产生正弦波。可以在fpga模拟正弦波-chdl 64 bit counter, using sine wave generated mif format. Sine wave can be simulated in FPGA
Platform: | Size: 268288 | Author: yyqdian | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[Wavelet] singt

Description: 实现了方波、正弦波、三角波的输出，同时在LCD模块中用状态机的方法实现LCD的对应显示：当输出正弦波，LCD显示“SIN”；当输出方波，LCD显示“REC”；当输出三角波，显示“TRI”；复位和其它位置波形显示“UNI”。-Realize a square wave, sine wave, triangle wave output, while in the LCD module using the state machine approach to achieve the corresponding LCD display: When the output sine wave, LCD display
Platform: | Size: 1062912 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] Triangle_Wave_generater

Description: 采用vhdl语言编程，基于quartus平台的三角波仿真。-Using VHDL language programming, based on the Quartus triangular wave simulation platform.
Platform: | Size: 2028544 | Author: 苏苏 | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
Platform: | Size: 675840 | Author: zzwuyu | Hits:

[VHDL-FPGA-Verilog] sin125

Description: 用FPGA实现DDS的信号发生器（正弦波125kHz）-Using FPGA to achieve DDS signal generator (sine wave 125kHz)
Platform: | Size: 196608 | Author: 杜海明 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

Description: 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度，由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the single-chip design, supplemented by the necessary analog circuits, based on the realization of a direct digital frequency synthesis (DDS) generator of sinusoidal No. Friends. The design of DDS chip AD9850 produced using 1KHZ ~ 10MHZ frequency range of sine wave, the AD811 control amplifier output voltage range of from single-chip AT89S52-conditioning step frequency control 1HZ. On this basis, the use of analog multiplier MC1496 has sinusoidal frequency modulation signal 1KHZ degree analog phase modulated signal generated by FPGA chip NRZ binary code, combined with the AD9850 to achieve phase shift keying PSK, ASK ASK, frequency Shift key town of FSK.
Platform: | Size: 208896 | Author: 何蓓 | Hits:

[VHDL-FPGA-Verilog] SPWM

Description: VHDL采用自然采样法写的SPWM，里面有正弦表，可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
Platform: | Size: 7168 | Author: zyb | Hits:

[SCM] signal

Description: verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
Platform: | Size: 5519360 | Author: ray | Hits:

[VHDL-FPGA-Verilog] dds

Description: fpga利用dds原理，产生正弦波，简单实用，成本低-fpga using dds principle, have a sine wave
Platform: | Size: 571392 | Author: wangjian | Hits:

[VHDL-FPGA-Verilog] sine_wave_generator_using_FPGA_implementation

Description: 该资料介绍了用FPGA实现正弦波发生器，原理是利用内置rom表，通过查询的方式实现输出，然后经过外部DAC输出，频率达到1MHz-The information on the sine wave generator using FPGA implementation, the principle is the use of built-in rom form, by querying the means to achieve the output, and then an external DAC output frequency of 1MHz
Platform: | Size: 2190336 | Author: 陈振林 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

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[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

[Embeded-SCM Develop] DDSforsinandcos

[VHDL-FPGA-Verilog] DDS234

[VHDL-FPGA-Verilog] box

[VHDL-FPGA-Verilog] sin_generator

[VHDL-FPGA-Verilog] DDS-320-modu

[VHDL-FPGA-Verilog] sine

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[Wavelet] singt

[VHDL-FPGA-Verilog] Triangle_Wave_generater

[VHDL-FPGA-Verilog] sine-generator

[VHDL-FPGA-Verilog] sin125

[VHDL-FPGA-Verilog] VHDL-ROM4

[Software Engineering] DDS-baseddesignofthesinusoidalsignalgenerator

[VHDL-FPGA-Verilog] SPWM

[SCM] signal

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] sine_wave_generator_using_FPGA_implementation

[VHDL-FPGA-Verilog] VHDL(sin)

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